35 	if (status == 0 && sha->dfsha->shactl.part.en == 1) {  in intel_sha_set_ctl_enable()
36 		while (sha->dfsha->shasts.part.busy) {  in intel_sha_set_ctl_enable()
40 	sha->dfsha->shactl.part.en = status;  in intel_sha_set_ctl_enable()
49 		sha->dfsha->sharldw0.full = lower_length;  in intel_sha_set_resume_length_dw0()
58 	sha->dfsha->sharldw1.full = upper_length;  in intel_sha_set_resume_length_dw1()
96 	self->dfsha->pibcs.part.peen = 0;  in intel_sha_device_run()
98 	self->dfsha->pibba.full = (uint32_t)buf_in;  in intel_sha_device_run()
104 	self->dfsha->pibs.full = aligned_buff_size;  in intel_sha_device_run()
106 	self->dfsha->pibcs.part.bscie = 1;  in intel_sha_device_run()
107 	self->dfsha->pibcs.part.teie = 0;  in intel_sha_device_run()
109 	self->dfsha->pibcs.part.peen = 1;  in intel_sha_device_run()
111 	if (self->dfsha->shactl.part.en) {  in intel_sha_device_run()
115 	self->dfsha->shactl.part.hrsm = state_u.part.hrsm;  in intel_sha_device_run()
119 		err = intel_sha_set_resume_length_dw0(self, self->dfsha->shaaldw0.full);  in intel_sha_device_run()
123 		err = intel_sha_set_resume_length_dw1(self, self->dfsha->shaaldw1.full);  in intel_sha_device_run()
127 		err = intel_sha_regs_cpy((void *)self->dfsha->initial_vector,  in intel_sha_device_run()
128 					 (void *)self->dfsha->sha_result,  in intel_sha_device_run()
129 					 sizeof(self->dfsha->initial_vector));  in intel_sha_device_run()
136 	if (self->dfsha->shactl.part.en) {  in intel_sha_device_run()
140 	self->dfsha->shactl.part.hfm = state_u.part.state;  in intel_sha_device_run()
143 	self->dfsha->pibfpi.full = buf_in_size;  in intel_sha_device_run()
167 		last_idx = (sizeof(self->dfsha->sha_result) / sizeof(uint32_t)) - 1;  in intel_sha_copy_hash()
171 				((uint32_t *)self->dfsha->sha_result)[last_idx - counter];  in intel_sha_copy_hash()
189 	while (self->dfsha->shasts.part.busy) {  in intel_sha_device_get_hash()
207 	self->dfsha->shactl.full = 0x0;  in intel_sha_compute()
208 	self->dfsha->shactl.part.algo = session->algo;  in intel_sha_compute()
211 	self->dfsha->shaaldw0 = session->sha_ctx.shaaldw0;  in intel_sha_compute()
212 	self->dfsha->shaaldw1 = session->sha_ctx.shaaldw1;  in intel_sha_compute()
214 	ret = intel_sha_regs_cpy((void *)self->dfsha->initial_vector,  in intel_sha_compute()
216 				 sizeof(self->dfsha->initial_vector));  in intel_sha_compute()
221 	ret = intel_sha_regs_cpy((void *)self->dfsha->sha_result,  in intel_sha_compute()
223 				 sizeof(self->dfsha->sha_result));  in intel_sha_compute()
254 		switch (self->dfsha->shactl.part.algo) {  in intel_sha_compute()
299 	self->dfsha->pibcs.part.peen = 0;  in intel_sha_device_set_hash_type()
315 	(void)memset((void *)self->dfsha, 0, sizeof(struct sha_hw_regs));  in intel_sha_device_free()
337 	.dfsha = (volatile struct sha_hw_regs *)DT_INST_REG_ADDR_BY_IDX(inst, 0)  \