Lines Matching +full:alarms +full:- +full:count
4 * SPDX-License-Identifier: Apache-2.0
51 while ((regs->SYNCBUSY.reg & TC_SYNCBUSY_MASK) != 0) { in wait_synchronization()
55 while ((regs->STATUS.reg & TC_STATUS_SYNCBUSY) != 0) { in wait_synchronization()
65 regs->READREQ.reg = TC_READREQ_RREQ | in read_synchronize_count()
69 regs->CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC; in read_synchronize_count()
78 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_start()
79 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_start()
85 tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER; in counter_sam0_tc32_start()
92 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_stop()
93 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_stop()
101 tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP; in counter_sam0_tc32_stop()
108 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_read()
109 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_read()
112 return tc->COUNT.reg; in counter_sam0_tc32_read()
125 struct counter_sam0_tc32_data *data = dev->data; in counter_sam0_tc32_relative_alarm()
126 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_relative_alarm()
127 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_relative_alarm()
134 before = tc->COUNT.reg; in counter_sam0_tc32_relative_alarm()
137 max = tc->CC[0].reg; in counter_sam0_tc32_relative_alarm()
139 target -= max; in counter_sam0_tc32_relative_alarm()
142 tc->CC[1].reg = target; in counter_sam0_tc32_relative_alarm()
144 tc->INTFLAG.reg = TC_INTFLAG_MC1; in counter_sam0_tc32_relative_alarm()
147 after = tc->COUNT.reg; in counter_sam0_tc32_relative_alarm()
150 if (tc->INTFLAG.bit.MC1) { in counter_sam0_tc32_relative_alarm()
167 counter_alarm_callback_t cb = data->ch.callback; in counter_sam0_tc32_relative_alarm()
169 tc->INTENCLR.reg = TC_INTENCLR_MC1; in counter_sam0_tc32_relative_alarm()
170 tc->INTFLAG.reg = TC_INTFLAG_MC1; in counter_sam0_tc32_relative_alarm()
171 data->ch.callback = NULL; in counter_sam0_tc32_relative_alarm()
173 cb(dev, 0, target, data->ch.user_data); in counter_sam0_tc32_relative_alarm()
178 tc->INTENSET.reg = TC_INTFLAG_MC1; in counter_sam0_tc32_relative_alarm()
185 struct counter_sam0_tc32_data *data = dev->data; in counter_sam0_tc32_set_alarm()
186 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_set_alarm()
187 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_set_alarm()
191 if (alarm_cfg->ticks > tc->CC[0].reg) { in counter_sam0_tc32_set_alarm()
192 return -EINVAL; in counter_sam0_tc32_set_alarm()
197 if (data->ch.callback) { in counter_sam0_tc32_set_alarm()
199 return -EBUSY; in counter_sam0_tc32_set_alarm()
202 data->ch.callback = alarm_cfg->callback; in counter_sam0_tc32_set_alarm()
203 data->ch.user_data = alarm_cfg->user_data; in counter_sam0_tc32_set_alarm()
205 if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) != 0) { in counter_sam0_tc32_set_alarm()
206 tc->CC[1].reg = alarm_cfg->ticks; in counter_sam0_tc32_set_alarm()
208 tc->INTFLAG.reg = TC_INTFLAG_MC1; in counter_sam0_tc32_set_alarm()
209 tc->INTENSET.reg = TC_INTFLAG_MC1; in counter_sam0_tc32_set_alarm()
211 counter_sam0_tc32_relative_alarm(dev, alarm_cfg->ticks); in counter_sam0_tc32_set_alarm()
222 struct counter_sam0_tc32_data *data = dev->data; in counter_sam0_tc32_cancel_alarm()
223 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_cancel_alarm()
224 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_cancel_alarm()
230 data->ch.callback = NULL; in counter_sam0_tc32_cancel_alarm()
231 tc->INTENCLR.reg = TC_INTENCLR_MC1; in counter_sam0_tc32_cancel_alarm()
232 tc->INTFLAG.reg = TC_INTFLAG_MC1; in counter_sam0_tc32_cancel_alarm()
241 struct counter_sam0_tc32_data *data = dev->data; in counter_sam0_tc32_set_top_value()
242 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_set_top_value()
243 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_set_top_value()
247 if (data->ch.callback) { in counter_sam0_tc32_set_top_value()
249 return -EBUSY; in counter_sam0_tc32_set_top_value()
252 if (top_cfg->callback) { in counter_sam0_tc32_set_top_value()
253 data->top_cb = top_cfg->callback; in counter_sam0_tc32_set_top_value()
254 data->top_user_data = top_cfg->user_data; in counter_sam0_tc32_set_top_value()
255 tc->INTENSET.reg = TC_INTFLAG_MC0; in counter_sam0_tc32_set_top_value()
257 tc->INTENCLR.reg = TC_INTFLAG_MC0; in counter_sam0_tc32_set_top_value()
260 tc->CC[0].reg = top_cfg->ticks; in counter_sam0_tc32_set_top_value()
262 if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) { in counter_sam0_tc32_set_top_value()
267 if (counter_sam0_tc32_read(dev) >= top_cfg->ticks) { in counter_sam0_tc32_set_top_value()
268 err = -ETIME; in counter_sam0_tc32_set_top_value()
269 if (top_cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) { in counter_sam0_tc32_set_top_value()
270 tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER; in counter_sam0_tc32_set_top_value()
274 tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER; in counter_sam0_tc32_set_top_value()
279 tc->INTFLAG.reg = TC_INTFLAG_MC0; in counter_sam0_tc32_set_top_value()
286 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_get_pending_int()
287 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_get_pending_int()
289 return tc->INTFLAG.reg & (TC_INTFLAG_MC0 | TC_INTFLAG_MC1); in counter_sam0_tc32_get_pending_int()
294 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_get_top_value()
295 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_get_top_value()
302 return tc->CC[0].reg; in counter_sam0_tc32_get_top_value()
307 struct counter_sam0_tc32_data *data = dev->data; in counter_sam0_tc32_isr()
308 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_isr()
309 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_isr()
310 uint8_t status = tc->INTFLAG.reg; in counter_sam0_tc32_isr()
313 tc->INTFLAG.reg = status; in counter_sam0_tc32_isr()
316 if (data->ch.callback) { in counter_sam0_tc32_isr()
317 counter_alarm_callback_t cb = data->ch.callback; in counter_sam0_tc32_isr()
319 tc->INTENCLR.reg = TC_INTENCLR_MC1; in counter_sam0_tc32_isr()
320 data->ch.callback = NULL; in counter_sam0_tc32_isr()
322 cb(dev, 0, tc->CC[1].reg, data->ch.user_data); in counter_sam0_tc32_isr()
327 if (data->top_cb) { in counter_sam0_tc32_isr()
328 data->top_cb(dev, data->top_user_data); in counter_sam0_tc32_isr()
335 const struct counter_sam0_tc32_config *const cfg = dev->config; in counter_sam0_tc32_initialize()
336 TcCount32 *tc = cfg->regs; in counter_sam0_tc32_initialize()
341 GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_GEN_GCLK0 | in counter_sam0_tc32_initialize()
345 *cfg->mclk |= cfg->mclk_mask; in counter_sam0_tc32_initialize()
348 GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 | in counter_sam0_tc32_initialize()
352 PM->APBCMASK.reg |= cfg->pm_apbcmask; in counter_sam0_tc32_initialize()
358 * having CC1 available for alarms. in counter_sam0_tc32_initialize()
360 tc->CTRLA.reg = TC_CTRLA_MODE_COUNT32 | in counter_sam0_tc32_initialize()
364 cfg->prescaler; in counter_sam0_tc32_initialize()
368 tc->WAVE.reg = TC_WAVE_WAVEGEN_MFRQ; in counter_sam0_tc32_initialize()
372 tc->INTENCLR.reg = TC_INTENCLR_MASK; in counter_sam0_tc32_initialize()
374 retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in counter_sam0_tc32_initialize()
380 tc->CC[0].reg = UINT32_MAX; in counter_sam0_tc32_initialize()
382 cfg->irq_config_func(dev); in counter_sam0_tc32_initialize()
384 tc->CTRLA.bit.ENABLE = 1; in counter_sam0_tc32_initialize()
388 tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP; in counter_sam0_tc32_initialize()