79 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_start()  local
85 	tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;  in counter_sam0_tc32_start()
86 	wait_synchronization(tc);  in counter_sam0_tc32_start()
93 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_stop()  local
101 	tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;  in counter_sam0_tc32_stop()
102 	wait_synchronization(tc);  in counter_sam0_tc32_stop()
109 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_read()  local
111 	read_synchronize_count(tc);  in counter_sam0_tc32_read()
112 	return tc->COUNT.reg;  in counter_sam0_tc32_read()
127 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_relative_alarm()  local
133 	read_synchronize_count(tc);  in counter_sam0_tc32_relative_alarm()
134 	before = tc->COUNT.reg;  in counter_sam0_tc32_relative_alarm()
137 	max = tc->CC[0].reg;  in counter_sam0_tc32_relative_alarm()
142 	tc->CC[1].reg = target;  in counter_sam0_tc32_relative_alarm()
143 	wait_synchronization(tc);  in counter_sam0_tc32_relative_alarm()
144 	tc->INTFLAG.reg = TC_INTFLAG_MC1;  in counter_sam0_tc32_relative_alarm()
146 	read_synchronize_count(tc);  in counter_sam0_tc32_relative_alarm()
147 	after = tc->COUNT.reg;  in counter_sam0_tc32_relative_alarm()
150 	if (tc->INTFLAG.bit.MC1) {  in counter_sam0_tc32_relative_alarm()
169 	tc->INTENCLR.reg = TC_INTENCLR_MC1;  in counter_sam0_tc32_relative_alarm()
170 	tc->INTFLAG.reg = TC_INTFLAG_MC1;  in counter_sam0_tc32_relative_alarm()
178 	tc->INTENSET.reg = TC_INTFLAG_MC1;  in counter_sam0_tc32_relative_alarm()
187 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_set_alarm()  local
191 	if (alarm_cfg->ticks > tc->CC[0].reg) {  in counter_sam0_tc32_set_alarm()
206 		tc->CC[1].reg = alarm_cfg->ticks;  in counter_sam0_tc32_set_alarm()
207 		wait_synchronization(tc);  in counter_sam0_tc32_set_alarm()
208 		tc->INTFLAG.reg = TC_INTFLAG_MC1;  in counter_sam0_tc32_set_alarm()
209 		tc->INTENSET.reg = TC_INTFLAG_MC1;  in counter_sam0_tc32_set_alarm()
224 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_cancel_alarm()  local
231 	tc->INTENCLR.reg = TC_INTENCLR_MC1;  in counter_sam0_tc32_cancel_alarm()
232 	tc->INTFLAG.reg = TC_INTFLAG_MC1;  in counter_sam0_tc32_cancel_alarm()
243 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_set_top_value()  local
255 		tc->INTENSET.reg = TC_INTFLAG_MC0;  in counter_sam0_tc32_set_top_value()
257 		tc->INTENCLR.reg = TC_INTFLAG_MC0;  in counter_sam0_tc32_set_top_value()
260 	tc->CC[0].reg = top_cfg->ticks;  in counter_sam0_tc32_set_top_value()
270 				tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;  in counter_sam0_tc32_set_top_value()
274 		tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;  in counter_sam0_tc32_set_top_value()
277 	wait_synchronization(tc);  in counter_sam0_tc32_set_top_value()
279 	tc->INTFLAG.reg = TC_INTFLAG_MC0;  in counter_sam0_tc32_set_top_value()
287 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_get_pending_int()  local
289 	return tc->INTFLAG.reg & (TC_INTFLAG_MC0 | TC_INTFLAG_MC1);  in counter_sam0_tc32_get_pending_int()
295 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_get_top_value()  local
302 	return tc->CC[0].reg;  in counter_sam0_tc32_get_top_value()
309 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_isr()  local
310 	uint8_t status = tc->INTFLAG.reg;  in counter_sam0_tc32_isr()
313 	tc->INTFLAG.reg = status;  in counter_sam0_tc32_isr()
319 			tc->INTENCLR.reg = TC_INTENCLR_MC1;  in counter_sam0_tc32_isr()
322 			cb(dev, 0, tc->CC[1].reg, data->ch.user_data);  in counter_sam0_tc32_isr()
336 	TcCount32 *tc = cfg->regs;  in counter_sam0_tc32_initialize()  local
344 	/* Enable TC clock in MCLK */  in counter_sam0_tc32_initialize()
360 	tc->CTRLA.reg = TC_CTRLA_MODE_COUNT32 |  in counter_sam0_tc32_initialize()
365 	wait_synchronization(tc);  in counter_sam0_tc32_initialize()
368 	tc->WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;  in counter_sam0_tc32_initialize()
372 	tc->INTENCLR.reg = TC_INTENCLR_MASK;  in counter_sam0_tc32_initialize()
380 	tc->CC[0].reg = UINT32_MAX;  in counter_sam0_tc32_initialize()
384 	tc->CTRLA.bit.ENABLE = 1;  in counter_sam0_tc32_initialize()
385 	wait_synchronization(tc);  in counter_sam0_tc32_initialize()
388 	tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;  in counter_sam0_tc32_initialize()
389 	wait_synchronization(tc);  in counter_sam0_tc32_initialize()