87 	uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);  in counter_dw_timer_irq_handler()  local
93 	sys_read32(reg_base + EOI_OFST);  in counter_dw_timer_irq_handler()
103 		sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_irq_handler()
117 	uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, timer_mmio);  in counter_dw_timer_start()  local
120 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_start()
123 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);  in counter_dw_timer_start()
124 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_start()
125 	sys_write32(FREE_RUNNING_MODE_VAL, reg_base + LOADCOUNT_OFST);  in counter_dw_timer_start()
128 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_start()
134 	uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, timer_mmio);  in counter_dw_timer_disable()  local
137 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_disable()
144 	uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);  in counter_dw_timer_get_top_value()  local
147 	top_val = sys_read32(reg_base + LOADCOUNT_OFST);  in counter_dw_timer_get_top_value()
154 	uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);  in counter_dw_timer_get_value()  local
157 	*ticks = sys_read32(reg_base + CURRENTVAL_OFST);  in counter_dw_timer_get_value()
165 	uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);  in counter_dw_timer_set_top_value()  local
191 		sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_set_top_value()
194 		sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_set_top_value()
201 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_set_top_value()
204 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);  in counter_dw_timer_set_top_value()
207 	sys_write32(top_cfg->ticks, reg_base + LOADCOUNT_OFST);  in counter_dw_timer_set_top_value()
208 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_set_top_value()
219 	uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);  in counter_dw_timer_set_alarm()  local
254 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_set_alarm()
257 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);  in counter_dw_timer_set_alarm()
258 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_set_alarm()
260 	sys_write32(alarm_cfg->ticks, reg_base + LOADCOUNT_OFST);  in counter_dw_timer_set_alarm()
261 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_set_alarm()
271 	uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio);  in counter_dw_timer_cancel_alarm()  local
277 	sys_write32(0, reg_base + CONTROLREG_OFST);  in counter_dw_timer_cancel_alarm()