23 #define CONTROLREG_OFST          0x8  macro
103 		sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_irq_handler()
120 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_start()
123 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);  in counter_dw_timer_start()
124 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_start()
128 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_start()
137 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_disable()
191 		sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_set_top_value()
194 		sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_set_top_value()
201 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_set_top_value()
204 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);  in counter_dw_timer_set_top_value()
208 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_set_top_value()
254 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_set_alarm()
257 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT);  in counter_dw_timer_set_alarm()
258 	sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT);  in counter_dw_timer_set_alarm()
261 	sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT);  in counter_dw_timer_set_alarm()
277 	sys_write32(0, reg_base + CONTROLREG_OFST);  in counter_dw_timer_cancel_alarm()