16 #define REG_IDR   0x00 /* ID and Revision Reg.   */
17 #define REG_CFG   0x10 /* Configuration Reg.     */
18 #define REG_INTE  0x14 /* Interrupt Enable Reg.  */
19 #define REG_ISTA  0x18 /* Interrupt Status Reg.  */
20 #define REG_CHEN  0x1C /* Channel Enable Reg.    */
21 #define REG_CTRL0 0x20 /* Channel 0 Control Reg. */
22 #define REG_RELD0 0x24 /* Channel 0 Reload Reg.  */
23 #define REG_CNTR0 0x28 /* Channel 0 Counter Reg. */
24 #define REG_CTRL1 0x30 /* Channel 1 Control Reg. */
25 #define REG_RELD1 0x34 /* Channel 1 Reload Reg.  */
26 #define REG_CNTR1 0x38 /* Channel 1 Counter Reg. */
27 #define REG_CTRL2 0x40 /* Channel 2 Control Reg. */
28 #define REG_RELD2 0x44 /* Channel 2 Reload Reg.  */
29 #define REG_CNTR2 0x48 /* Channel 2 Counter Reg. */
30 #define REG_CTRL3 0x50 /* Channel 3 Control Reg. */
31 #define REG_RELD3 0x54 /* Channel 3 Reload Reg.  */
32 #define REG_CNTR3 0x58 /* Channel 3 Counter Reg. */
131 	uint32_t reg;  in counter_atcpit100_init()  local
137 	reg = CTRL_CH_MODE_32BIT | CTRL_CH_SRC_PCLK;  in counter_atcpit100_init()
138 	sys_write32(reg, PIT_CH_CTRL(dev, 0));  in counter_atcpit100_init()
139 	sys_write32(reg, PIT_CH_CTRL(dev, 1));  in counter_atcpit100_init()
140 	sys_write32(reg, PIT_CH_CTRL(dev, 2));  in counter_atcpit100_init()
141 	sys_write32(reg, PIT_CH_CTRL(dev, 3));  in counter_atcpit100_init()
148 	reg = config->info.max_top_value * config->divider;  in counter_atcpit100_init()
151 	sys_write32((reg - 1), PIT_CH_RELD(dev, 3));  in counter_atcpit100_init()
164 	uint32_t reg;  in atcpit100_start()  local
169 	reg = sys_read32(PIT_CHEN(dev));  in atcpit100_start()
170 	reg |= TIMER0_CHANNEL(3);  in atcpit100_start()
171 	sys_write32(reg, PIT_CHEN(dev));  in atcpit100_start()
182 	uint32_t reg;  in atcpit100_stop()  local
187 	reg = sys_read32(PIT_INTE(dev));  in atcpit100_stop()
188 	reg &= ~TIMER0_CHANNEL(3);  in atcpit100_stop()
189 	sys_write32(reg, PIT_INTE(dev));  in atcpit100_stop()
192 	reg = sys_read32(PIT_CHEN(dev));  in atcpit100_stop()
193 	reg &= ~TIMER0_CHANNEL(3);  in atcpit100_stop()
194 	sys_write32(reg, PIT_CHEN(dev));  in atcpit100_stop()
223 	uint32_t top, now_cnt, remain_cnt, alarm_cnt, flags, reg;  in atcpit100_set_alarm()  local
264 			reg = alarm_cnt - now_cnt;  in atcpit100_set_alarm()
268 			reg = alarm_cnt + remain_cnt;  in atcpit100_set_alarm()
271 		if (reg > max_rel_val) {  in atcpit100_set_alarm()
282 			reg = 1;  in atcpit100_set_alarm()
290 		reg = alarm_cnt - (now_cnt - remain_cnt);  in atcpit100_set_alarm()
294 	sys_write32((reg - 1), PIT_CH_RELD(dev, chan_id));  in atcpit100_set_alarm()
297 	reg = sys_read32(PIT_INTE(dev));  in atcpit100_set_alarm()
298 	reg |= TIMER0_CHANNEL(chan_id);  in atcpit100_set_alarm()
299 	sys_write32(reg, PIT_INTE(dev));  in atcpit100_set_alarm()
302 	reg = sys_read32(PIT_CHEN(dev));  in atcpit100_set_alarm()
303 	reg |= TIMER0_CHANNEL(chan_id);  in atcpit100_set_alarm()
304 	sys_write32(reg, PIT_CHEN(dev));  in atcpit100_set_alarm()
316 	uint32_t reg;  in atcpit100_cancel_alarm()  local
325 	reg = sys_read32(PIT_INTE(dev));  in atcpit100_cancel_alarm()
326 	reg &= ~TIMER0_CHANNEL(chan_id);  in atcpit100_cancel_alarm()
327 	sys_write32(reg, PIT_INTE(dev));  in atcpit100_cancel_alarm()
330 	reg = sys_read32(PIT_CHEN(dev));  in atcpit100_cancel_alarm()
331 	reg &= ~TIMER0_CHANNEL(chan_id);  in atcpit100_cancel_alarm()
332 	sys_write32(reg, PIT_CHEN(dev));  in atcpit100_cancel_alarm()
349 	uint32_t ticks, reg, reset_counter = 1;  in atcpit100_set_top_value()  local
368 		reg = sys_read32(PIT_INTE(dev));  in atcpit100_set_top_value()
369 		reg &= ~TIMER0_CHANNEL(3);  in atcpit100_set_top_value()
370 		sys_write32(reg, PIT_INTE(dev));  in atcpit100_set_top_value()
376 		reg = sys_read32(PIT_INTE(dev));  in atcpit100_set_top_value()
377 		reg |= TIMER0_CHANNEL(3);  in atcpit100_set_top_value()
378 		sys_write32(reg, PIT_INTE(dev));  in atcpit100_set_top_value()
395 	reg = cfg->ticks * config->divider;  in atcpit100_set_top_value()
396 	sys_write32((reg - 1), PIT_CH_RELD(dev, 3));  in atcpit100_set_top_value()
400 		reg = sys_read32(PIT_CHEN(dev));  in atcpit100_set_top_value()
401 		reg &= ~TIMER0_CHANNEL(3);  in atcpit100_set_top_value()
402 		sys_write32(reg, PIT_CHEN(dev));  in atcpit100_set_top_value()
408 		reg = sys_read32(PIT_INTE(dev));  in atcpit100_set_top_value()
409 		reg |= TIMER0_CHANNEL(3);  in atcpit100_set_top_value()
410 		sys_write32(reg, PIT_INTE(dev));  in atcpit100_set_top_value()
413 		reg = sys_read32(PIT_CHEN(dev));  in atcpit100_set_top_value()
414 		reg |= TIMER0_CHANNEL(3);  in atcpit100_set_top_value()
415 		sys_write32(reg, PIT_CHEN(dev));  in atcpit100_set_top_value()
425 	uint32_t reg = sys_read32(PIT_ISTA(dev));  in atcpit100_get_pending_int()  local
427 	reg &= (TIMER0_CHANNEL(0) | TIMER0_CHANNEL(1) |  in atcpit100_get_pending_int()
430 	return !(!reg);  in atcpit100_get_pending_int()