52 	if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) ||  in get_pllsrc_frequency()
53 	    (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) ||  in get_pllsrc_frequency()
54 	    (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID)) {  in get_pllsrc_frequency()
56 	} else if ((IS_ENABLED(STM32_PLL_SRC_HSE) && pll_id == PLL1_ID) ||  in get_pllsrc_frequency()
57 		   (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) ||  in get_pllsrc_frequency()
58 		   (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID)) {  in get_pllsrc_frequency()
60 	} else if ((IS_ENABLED(STM32_PLL_SRC_CSI) && pll_id == PLL1_ID) ||  in get_pllsrc_frequency()
61 		   (IS_ENABLED(STM32_PLL2_SRC_CSI) && pll_id == PLL2_ID) ||  in get_pllsrc_frequency()
62 		   (IS_ENABLED(STM32_PLL3_SRC_CSI) && pll_id == PLL3_ID)) {  in get_pllsrc_frequency()
126 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||  in enabled_clock()
127 	    ((src_clk == STM32_SRC_HSI) && IS_ENABLED(STM32_HSI_ENABLED)) ||  in enabled_clock()
128 	    ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||  in enabled_clock()
129 	    ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||  in enabled_clock()
130 	    ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||  in enabled_clock()
131 	    ((src_clk == STM32_SRC_CSI) && IS_ENABLED(STM32_CSI_ENABLED)) ||  in enabled_clock()
132 	    ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||  in enabled_clock()
133 	    ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||  in enabled_clock()
134 	    ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) ||  in enabled_clock()
135 	    ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||  in enabled_clock()
136 	    ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||  in enabled_clock()
137 	    ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||  in enabled_clock()
138 	    ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||  in enabled_clock()
139 	    ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||  in enabled_clock()
140 	    ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {  in enabled_clock()
451 	if (IS_ENABLED(STM32_PLL_SRC_HSE)) {  in set_up_plls()
454 	} else if (IS_ENABLED(STM32_PLL_SRC_CSI)) {  in set_up_plls()
457 	} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {  in set_up_plls()
482 	if (IS_ENABLED(STM32_PLL_P_ENABLED)) {  in set_up_plls()
487 	if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {  in set_up_plls()
492 	if (IS_ENABLED(STM32_PLL_R_ENABLED)) {  in set_up_plls()
507 	if (IS_ENABLED(STM32_PLL2_SRC_HSE)) {  in set_up_plls()
509 	} else if (IS_ENABLED(STM32_PLL2_SRC_CSI)) {  in set_up_plls()
511 	} else if (IS_ENABLED(STM32_PLL2_SRC_HSI)) {  in set_up_plls()
535 	if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {  in set_up_plls()
540 	if (IS_ENABLED(STM32_PLL2_Q_ENABLED)) {  in set_up_plls()
545 	if (IS_ENABLED(STM32_PLL2_R_ENABLED)) {  in set_up_plls()
561 	if (IS_ENABLED(STM32_PLL3_SRC_HSE)) {  in set_up_plls()
563 	} else if (IS_ENABLED(STM32_PLL3_SRC_CSI)) {  in set_up_plls()
565 	} else if (IS_ENABLED(STM32_PLL3_SRC_HSI)) {  in set_up_plls()
589 	if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {  in set_up_plls()
594 	if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {  in set_up_plls()
599 	if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {  in set_up_plls()
619 	if (IS_ENABLED(STM32_HSE_ENABLED)) {  in set_up_fixed_clock_sources()
621 		if (IS_ENABLED(STM32_HSE_BYPASS)) {  in set_up_fixed_clock_sources()
634 	if (IS_ENABLED(STM32_HSI_ENABLED)) {  in set_up_fixed_clock_sources()
635 		if (IS_ENABLED(STM32_PLL_SRC_HSI) ||  in set_up_fixed_clock_sources()
636 			IS_ENABLED(STM32_PLL2_SRC_HSI) || IS_ENABLED(STM32_PLL3_SRC_HSI)) {  in set_up_fixed_clock_sources()
652 	if (IS_ENABLED(STM32_LSE_ENABLED)) {  in set_up_fixed_clock_sources()
664 		if (IS_ENABLED(STM32_LSE_BYPASS)) {  in set_up_fixed_clock_sources()
678 	if (IS_ENABLED(STM32_CSI_ENABLED)) {  in set_up_fixed_clock_sources()
679 		if (IS_ENABLED(STM32_PLL_SRC_CSI) ||  in set_up_fixed_clock_sources()
680 			IS_ENABLED(STM32_PLL2_SRC_CSI) || IS_ENABLED(STM32_PLL3_SRC_CSI)) {  in set_up_fixed_clock_sources()
693 	if (IS_ENABLED(STM32_LSI_ENABLED)) {  in set_up_fixed_clock_sources()
700 	if (IS_ENABLED(STM32_HSI48_ENABLED)) {  in set_up_fixed_clock_sources()
742 	if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {  in stm32_clock_control_init()
747 	} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {  in stm32_clock_control_init()
752 	} else if (IS_ENABLED(STM32_SYSCLK_SRC_CSI)) {  in stm32_clock_control_init()
757 	} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {  in stm32_clock_control_init()