4  * SPDX-License-Identifier: Apache-2.0
33 	const struct clock_control_si32_pll_config *config = dev->config;  in clock_control_si32_pll_on()
34 	struct clock_control_si32_pll_data *data = dev->data;  in clock_control_si32_pll_on()  local
36 	if (data->freq == 0) {  in clock_control_si32_pll_on()
37 		return -ENOTSUP;  in clock_control_si32_pll_on()
42 	if (data->freq > 80000000) {  in clock_control_si32_pll_on()
44 	} else if (data->freq > 76500000) {  in clock_control_si32_pll_on()
46 	} else if (data->freq > 62000000) {  in clock_control_si32_pll_on()
48 	} else if (data->freq > 49500000) {  in clock_control_si32_pll_on()
50 	} else if (data->freq > 35000000) {  in clock_control_si32_pll_on()
52 	} else if (data->freq > 23000000) {  in clock_control_si32_pll_on()
55 		return -ENOTSUP;  in clock_control_si32_pll_on()
61 	const uint32_t div_n = (data->freq / source_clock_freq) * (div_m + 1) - 1;  in clock_control_si32_pll_on()
64 		return -ENOTSUP;  in clock_control_si32_pll_on()
68 	SI32_PLL_A_initialize(config->pll, 0x00, 0x00, 0x00, 0x000FFF0);  in clock_control_si32_pll_on()
69 	SI32_PLL_A_set_numerator(config->pll, div_n);  in clock_control_si32_pll_on()
70 	SI32_PLL_A_set_denominator(config->pll, div_m);  in clock_control_si32_pll_on()
72 	SI32_PLL_A_select_reference_clock_source_lp0oscdiv(config->pll);  in clock_control_si32_pll_on()
75 	SI32_PLL_A_select_disable_dco_output(config->pll);  in clock_control_si32_pll_on()
76 	SI32_PLL_A_set_frequency_adjuster_value(config->pll, 0xFFF);  in clock_control_si32_pll_on()
77 	SI32_PLL_A_set_output_frequency_range(config->pll, dco_range);  in clock_control_si32_pll_on()
80 	SI32_PLL_A_select_dco_frequency_lock_mode(config->pll);  in clock_control_si32_pll_on()
81 	while (!(SI32_PLL_A_is_locked(config->pll) ||  in clock_control_si32_pll_on()
82 		 SI32_PLL_A_is_saturation_low_interrupt_pending(config->pll) ||  in clock_control_si32_pll_on()
83 		 SI32_PLL_A_is_saturation_high_interrupt_pending(config->pll)))  in clock_control_si32_pll_on()
92 	return -ENOTSUP;  in clock_control_si32_pll_off()
96 					   uint32_t *rate)  in clock_control_si32_pll_get_rate()  argument
98 	struct clock_control_si32_pll_data *data = dev->data;  in clock_control_si32_pll_get_rate()  local
100 	*rate = data->freq;  in clock_control_si32_pll_get_rate()
108 	struct clock_control_si32_pll_data *data = dev->data;  in clock_control_si32_pll_set_rate()  local
109 	const uint32_t *rate = rate_;  in clock_control_si32_pll_set_rate()  local
111 	data->freq = *rate;  in clock_control_si32_pll_set_rate()
134 static struct clock_control_si32_pll_data data = {  variable
138 DEVICE_DT_INST_DEFINE(0, clock_control_si32_pll_init, NULL, &data, &config, PRE_KERNEL_1,