33 int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable)  in rcar_cpg_mstp_clock_endisable()  argument
35 	uint32_t reg = module / 100;  in rcar_cpg_mstp_clock_endisable()
36 	uint32_t bit = module % 100;  in rcar_cpg_mstp_clock_endisable()
40 	__ASSERT((bit < 32) && reg < ARRAY_SIZE(mstpcr), "Invalid module number for cpg clock: %d",  in rcar_cpg_mstp_clock_endisable()
41 		 module);  in rcar_cpg_mstp_clock_endisable()
61 	uint32_t module = (uintptr_t)key;  in cmp_cpg_clk_info_table_items()  local
63 	if (e->module == module) {  in cmp_cpg_clk_info_table_items()
65 	} else if (e->module < module) {  in cmp_cpg_clk_info_table_items()
84 		LOG_ERR("%s: can't find clk info (domain %u module %u)", dev->name, domain, id);  in rcar_cpg_find_clk_info_by_module_id()
111 		divider = data->get_div_helper(reg_val, clk_info->module);  in rcar_cpg_get_divider()
200 			 * - we don't have this module in a table (for some of call chains of  in rcar_cpg_change_children_in_out_freq()
205 				"module %u! Please, revise logic related to obtaining divider or "  in rcar_cpg_change_children_in_out_freq()
207 				dev->name, children_list->domain, children_list->module);  in rcar_cpg_change_children_in_out_freq()
233 	clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module);  in rcar_cpg_get_rate()
245 		LOG_ERR("%s: clk (domain %u module %u) error (%lld) during getting out frequency",  in rcar_cpg_get_rate()
246 			dev->name, clk->domain, clk->module, ret);  in rcar_cpg_get_rate()
249 		LOG_ERR("%s: clk (domain %u module %u) frequency bigger then max uint value",  in rcar_cpg_get_rate()
250 			dev->name, clk->domain, clk->module);  in rcar_cpg_get_rate()
269 	uint32_t module;  in rcar_cpg_set_rate()  local
278 	clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module);  in rcar_cpg_set_rate()
285 			LOG_ERR("%s: parent isn't present for module clock, module id %u",  in rcar_cpg_set_rate()
286 				dev->name, clk_info->module);  in rcar_cpg_set_rate()
292 	module = clk_info->module;  in rcar_cpg_set_rate()
313 	ret = data->set_rate_helper(module, &divider, &div_mask);  in rcar_cpg_set_rate()
326 			LOG_ERR("%s: clock (domain %u module %u) register cfg freq (%lld) "  in rcar_cpg_set_rate()
328 				dev->name, clk->domain, clk->module, out_rate, u_rate);  in rcar_cpg_set_rate()
359 			/* check if an array is sorted by module id or not */  in rcar_cpg_build_clock_relationship()
360 			if (prev_mod_id >= item->module) {  in rcar_cpg_build_clock_relationship()
362 					"ascending order by module id field, domain %u "  in rcar_cpg_build_clock_relationship()
363 					"module id %u",  in rcar_cpg_build_clock_relationship()
364 					dev->name, item->domain, item->module);  in rcar_cpg_build_clock_relationship()
368 			prev_mod_id = item->module;  in rcar_cpg_build_clock_relationship()
378 					"domain %u module id %u",  in rcar_cpg_build_clock_relationship()
379 					dev->name, item->domain, item->module);  in rcar_cpg_build_clock_relationship()
385 					"module id %u, parent for the clock has been already set",  in rcar_cpg_build_clock_relationship()
386 					dev->name, item->domain, item->module);  in rcar_cpg_build_clock_relationship()
418 					"domain %u module %u! Please, review correctness of data "  in rcar_cpg_update_all_in_out_freq()
420 					dev->name, item->domain, item->module);  in rcar_cpg_update_all_in_out_freq()