Lines Matching full:domain
73 rcar_cpg_find_clk_info_by_module_id(const struct device *dev, uint32_t domain, uint32_t id) in rcar_cpg_find_clk_info_by_module_id() argument
77 struct cpg_clk_info_table *table = data->clk_info_table[domain]; in rcar_cpg_find_clk_info_by_module_id()
78 uint32_t table_size = data->clk_info_table_size[domain]; in rcar_cpg_find_clk_info_by_module_id()
84 LOG_ERR("%s: can't find clk info (domain %u module %u)", dev->name, domain, id); in rcar_cpg_find_clk_info_by_module_id()
97 if (clk_info->domain == CPG_MOD) { in rcar_cpg_get_divider()
204 LOG_ERR("%s: error during getting divider from clock register, domain %u " in rcar_cpg_change_children_in_out_freq()
207 dev->name, children_list->domain, children_list->module); in rcar_cpg_change_children_in_out_freq()
233 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in rcar_cpg_get_rate()
245 LOG_ERR("%s: clk (domain %u module %u) error (%lld) during getting out frequency", in rcar_cpg_get_rate()
246 dev->name, clk->domain, clk->module, ret); in rcar_cpg_get_rate()
249 LOG_ERR("%s: clk (domain %u module %u) frequency bigger then max uint value", in rcar_cpg_get_rate()
250 dev->name, clk->domain, clk->module); in rcar_cpg_get_rate()
278 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in rcar_cpg_set_rate()
283 if (clk_info->domain == CPG_MOD) { in rcar_cpg_set_rate()
326 LOG_ERR("%s: clock (domain %u module %u) register cfg freq (%lld) " in rcar_cpg_set_rate()
328 dev->name, clk->domain, clk->module, out_rate, u_rate); in rcar_cpg_set_rate()
342 uint32_t domain; in rcar_cpg_build_clock_relationship() local
351 for (domain = 0; domain < CPG_NUM_DOMAINS; domain++) { in rcar_cpg_build_clock_relationship()
354 struct cpg_clk_info_table *item = data->clk_info_table[domain]; in rcar_cpg_build_clock_relationship()
356 for (idx = 0; idx < data->clk_info_table_size[domain]; idx++, item++) { in rcar_cpg_build_clock_relationship()
362 "ascending order by module id field, domain %u " in rcar_cpg_build_clock_relationship()
364 dev->name, item->domain, item->module); in rcar_cpg_build_clock_relationship()
378 "domain %u module id %u", in rcar_cpg_build_clock_relationship()
379 dev->name, item->domain, item->module); in rcar_cpg_build_clock_relationship()
384 LOG_ERR("%s: trying to set another parent for a clock, domain %u " in rcar_cpg_build_clock_relationship()
386 dev->name, item->domain, item->module); in rcar_cpg_build_clock_relationship()
402 uint32_t domain; in rcar_cpg_update_all_in_out_freq() local
411 for (domain = 0; domain < CPG_NUM_DOMAINS; domain++) { in rcar_cpg_update_all_in_out_freq()
413 struct cpg_clk_info_table *item = data->clk_info_table[domain]; in rcar_cpg_update_all_in_out_freq()
415 for (idx = 0; idx < data->clk_info_table_size[domain]; idx++, item++) { in rcar_cpg_update_all_in_out_freq()
418 "domain %u module %u! Please, review correctness of data " in rcar_cpg_update_all_in_out_freq()
420 dev->name, item->domain, item->module); in rcar_cpg_update_all_in_out_freq()