4  * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcx_clock.h>
26 	((struct cdcg_reg *)((const struct npcx_pcc_config *)(dev)->config)->base_cdcg)
29 	((struct pmc_reg *)((const struct npcx_pcc_config *)(dev)->config)->base_pmc)
39 	const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;  in npcx_clock_control_on()
41 	if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) {  in npcx_clock_control_on()
42 		return -EINVAL;  in npcx_clock_control_on()
45 	/* Clear related PD (Power-Down) bit of module to turn on clock */  in npcx_clock_control_on()
46 	NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) &= ~(BIT(clk_cfg->bit));  in npcx_clock_control_on()
55 	const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;  in npcx_clock_control_off()
57 	if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT) {  in npcx_clock_control_off()
58 		return -EINVAL;  in npcx_clock_control_off()
61 	/* Set related PD (Power-Down) bit of module to turn off clock */  in npcx_clock_control_off()
62 	NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) |= BIT(clk_cfg->bit);  in npcx_clock_control_off()
73 	switch (clk_cfg->bus) {  in npcx_clock_control_get_subsys_rate()
114 		return -EINVAL;  in npcx_clock_control_get_subsys_rate()
129 	/* Add 'Disable High-Frequency' flag (ie. 'deep sleep' mode) */  in npcx_clock_control_turn_on_system_sleep()
132 		/* Add 'Instant Wake-up' flag if sleep time is within 200 ms */  in npcx_clock_control_turn_on_system_sleep()
138 	inst_pmc->PMCSR = pm_flags;  in npcx_clock_control_turn_on_system_sleep()
146 	inst_pmc->PMCSR = 0;  in npcx_clock_control_turn_off_system_sleep()
203 	const uint32_t pmc_base = ((const struct npcx_pcc_config *)dev->config)->base_pmc;  in npcx_clock_control_init()
206 		inst_cdcg->LFCGCTL2 |= BIT(NPCX_LFCGCTL2_XT_OSC_SL_EN);  in npcx_clock_control_init()
214 	if (inst_cdcg->HFCGN != HFCGN_VAL || inst_cdcg->HFCGML != HFCGML_VAL  in npcx_clock_control_init()
215 			|| inst_cdcg->HFCGMH != HFCGMH_VAL) {  in npcx_clock_control_init()
220 		inst_cdcg->HFCGN  = HFCGN_VAL;  in npcx_clock_control_init()
221 		inst_cdcg->HFCGML = HFCGML_VAL;  in npcx_clock_control_init()
222 		inst_cdcg->HFCGMH = HFCGMH_VAL;  in npcx_clock_control_init()
225 		inst_cdcg->HFCGCTRL |= BIT(NPCX_HFCGCTRL_LOAD);  in npcx_clock_control_init()
227 		while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG)) {  in npcx_clock_control_init()
233 	inst_cdcg->HFCGP   = VAL_HFCGP;  in npcx_clock_control_init()
234 	inst_cdcg->HFCBCD  = VAL_HFCBCD;  in npcx_clock_control_init()
235 	inst_cdcg->HFCBCD1 = VAL_HFCBCD1;  in npcx_clock_control_init()
236 	inst_cdcg->HFCBCD2 = VAL_HFCBCD2;  in npcx_clock_control_init()
238 	inst_cdcg->HFCBCD3 = VAL_HFCBCD3;  in npcx_clock_control_init()
242 	 * Power-down (turn off clock) the modules initially for better  in npcx_clock_control_init()