213 	struct clk_cfg_t *priv;  in npcm_clock_control_on()  local
216 	priv = npcm_get_cfg(sub_system);  in npcm_clock_control_on()
217 	if (!priv) {  in npcm_clock_control_on()
223 	NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) &=  in npcm_clock_control_on()
224 		~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id)));  in npcm_clock_control_on()
232 	struct clk_cfg_t *priv;  in npcm_clock_control_off()  local
235 	priv = npcm_get_cfg(sub_system);  in npcm_clock_control_off()
236 	if (!priv) {  in npcm_clock_control_off()
242 	NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) |=  in npcm_clock_control_off()
243 		~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id)));  in npcm_clock_control_off()
252 	struct clk_cfg_t *priv;  in npcm_clock_control_get_subsys_rate()  local
254 	priv = npcm_get_cfg(sub_system);  in npcm_clock_control_get_subsys_rate()
255 	if (!priv) {  in npcm_clock_control_get_subsys_rate()
260 	switch (priv->bus) {  in npcm_clock_control_get_subsys_rate()
312 	struct cdcg_reg *const priv = (struct cdcg_reg *)(DRV_CONFIG(dev)->base_cdcg);  in npcm_clock_control_init()  local
333 	if (priv->hfcgn != freq_p->hfcgn || priv->hfcgml != freq_p->hfcgml ||  in npcm_clock_control_init()
334 	    priv->hfcgmh != freq_p->hfcgmh) {  in npcm_clock_control_init()
339 		priv->hfcgn = freq_p->hfcgn;  in npcm_clock_control_init()
340 		priv->hfcgml = freq_p->hfcgml;  in npcm_clock_control_init()
341 		priv->hfcgmh = freq_p->hfcgmh;  in npcm_clock_control_init()
344 		priv->hfcgctrl |= BIT(NPCM_HFCGCTRL_LOAD);  in npcm_clock_control_init()
346 		while (sys_test_bit(priv->hfcgctrl, NPCM_HFCGCTRL_CLK_CHNG))  in npcm_clock_control_init()
351 	priv->hfcgp = (FPRED_VAL << 4) | AHB6DIV_VAL;  in npcm_clock_control_init()
352 	priv->hfcbcd = APB1DIV_VAL | (APB2DIV_VAL << 4);  in npcm_clock_control_init()
353 	priv->hfcbcd1 = (I3CDIV_VAL << 2) | FIUDIV_VAL;  in npcm_clock_control_init()
354 	priv->hfcbcd2 = APB3DIV_VAL;  in npcm_clock_control_init()