Lines Matching refs:uint32_t
54 volatile uint32_t sys_mem_remap; /* System memory remap */
55 volatile uint32_t p_reset_ctrl; /* Peripheral reset control */
56 volatile uint32_t sys_pll_ctrl; /* System PLL control */
57 volatile const uint32_t sys_pll_stat; /* System PLL status */
58 volatile uint32_t usb_pll_ctrl; /* USB PLL control */
59 volatile const uint32_t usb_pll_stat; /* USB PLL status */
60 volatile const uint32_t reserved1;
61 volatile uint32_t rtc_osc_ctrl; /* RTC oscillator control */
62 volatile uint32_t sys_osc_ctrl; /* System oscillator control */
63 volatile uint32_t wdt_osc_ctrl; /* Watchdog oscillator
66 volatile uint32_t irc_ctrl; /* IRC Control */
67 volatile const uint32_t reserved2;
68 volatile uint32_t sys_rst_stat; /* System reset status */
69 volatile const uint32_t reserved3[3];
70 volatile uint32_t sys_pll_clk_sel; /* System PLL clock source */
71 volatile uint32_t sys_pll_clk_uen; /* System PLL source update */
72 volatile uint32_t usb_pll_clk_sel; /* USB PLL clock source */
73 volatile uint32_t usb_pll_clk_uen; /* USB PLL clock source
76 volatile const uint32_t reserved4[8];
77 volatile uint32_t main_clk_sel; /* Main clock select */
78 volatile uint32_t main_clk_uen; /* Main clock update */
79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
80 volatile const uint32_t reserved5;
81 volatile uint32_t sys_ahb_clk_ctrl; /* System clock control */
82 volatile const uint32_t reserved6[4];
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
85 volatile uint32_t ssp1_clk_div; /* SSP1 clock divider */
86 volatile uint32_t frg_clk_div; /* USART 1-4 fractional baud
89 volatile const uint32_t reserved7[7];
90 volatile uint32_t usb_clk_sel; /* USB clock select */
91 volatile uint32_t usb_clk_uen; /* USB clock update */
92 volatile uint32_t usb_clk_div; /* USB clock divider */
93 volatile const uint32_t reserved8[5];
94 volatile uint32_t clk_out_sel; /* CLKOUT source select */
95 volatile uint32_t clk_out_uen; /* CLKOUT source update */
96 volatile uint32_t clk_out_div; /* CLKOUT divider */
97 volatile const uint32_t reserved9;
98 volatile uint32_t uart_frg_div; /* USART1-4 fractional
101 volatile uint32_t uart_frg_mult; /* USART1-4 fractional
104 volatile const uint32_t reserved10;
105 volatile uint32_t ext_trace_cmd; /* External trace buffer
108 volatile const uint32_t pio_por_cap[3]; /* CLKOUT source select */
109 volatile const uint32_t reserved11[10];
110 volatile uint32_t iocon_clk_div[7]; /* IOCON clock divider */
111 volatile uint32_t bod_ctrl; /* Brown-out detect control */
112 volatile uint32_t sys_tck_cal; /* System tick calibration */
113 volatile const uint32_t reserved12[6];
114 volatile uint32_t irq_latency; /* IRQ latency */
115 volatile uint32_t nmi_src; /* NMI source control */
116 volatile uint32_t pint_sel[8]; /* GPIO pin interrupt select */
117 volatile uint32_t usb_clk_ctrl; /* USB clock control */
118 volatile const uint32_t usb_clk_stat; /* USB clock status */
119 volatile uint32_t reserved13[25];
120 volatile uint32_t starterp0; /* Start logic 0 int wake-up */
121 volatile const uint32_t reserved14[3];
122 volatile uint32_t starterp1; /* Start logic 1 int wake-up */
123 volatile const uint32_t reserved15[6];
124 volatile uint32_t pd_sleep_cfg; /* Deep-sleep power-down
127 volatile uint32_t pd_awake_cfg; /* Power-down states for
130 volatile uint32_t pd_run_cfg; /* Power configuration */
131 volatile const uint32_t reserved16[110];
132 volatile const uint32_t device_id; /* Device identifier */