Lines Matching +full:1000 +full:u
20 uint32_t arefclkdiv = 0U; in get_ref_clk()
21 uint32_t ref_clk = 0U; in get_ref_clk()
22 uint32_t mdiv = 0U; in get_ref_clk()
23 uint32_t pllglob_val = 0U; in get_ref_clk()
24 uint32_t pllm_val = 0U; in get_ref_clk()
63 LOG_DBG("%s: ref_clk %u\n", __func__, ref_clk); in get_ref_clk()
72 uint32_t clock_val = 0U; in get_clk_freq()
73 uint32_t clk_psrc = 0U; in get_clk_freq()
74 uint32_t pllcx_div = 0U; in get_clk_freq()
113 LOG_DBG("%s: clock source %lu and its value %u\n", in get_clk_freq()
159 uint32_t ctr_reg = 0U; in get_mpu_clk()
160 uint32_t clock_val = 0U; in get_mpu_clk()
238 * In ATF, the qspi clock is divided by 1000 and loaded in scratch cold register 0 in get_qspi_clk()
239 * So in Zephyr, reverting back the clock frequency by multiplying by 1000. in get_qspi_clk()
241 return (ref_clk * 1000); in get_qspi_clk()