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12 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
13 #define BQ24190_REG_ISC_EN_HIZ_SHIFT 7
20 #define BQ24190_REG_POC_RESET_MASK BIT(7)
21 #define BQ24190_REG_POC_RESET_SHIFT 7
40 #define BQ24190_REG_CCC_ICHG_MASK GENMASK(7, 2)
51 #define BQ24190_REG_PCTCC_IPRECHG_MASK GENMASK(7, 4)
66 #define BQ24190_REG_CVC_VREG_MASK GENMASK(7, 2)
79 #define BQ24190_REG_CTTC_EN_TERM_MASK BIT(7)
80 #define BQ24190_REG_CTTC_EN_TERM_SHIFT 7
94 #define BQ24190_REG_ICTRC_BAT_COMP_MASK GENMASK(7, 5)
103 #define BQ24190_REG_MOC_DPDM_EN_MASK BIT(7)
104 #define BQ24190_REG_MOC_DPDM_EN_SHIFT 7
116 #define BQ24190_REG_SS_VBUS_STAT_MASK GENMASK(7, 6)
135 #define BQ24190_REG_F_WATCHDOG_FAULT_MASK BIT(7)
136 #define BQ24190_REG_F_WATCHDOG_FAULT_SHIFT 7