Lines Matching +full:5 +full:- +full:7
4 * SPDX-License-Identifier: Apache-2.0
12 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
13 #define BQ24190_REG_ISC_EN_HIZ_SHIFT 7
18 /* Power-On Configuration */
20 #define BQ24190_REG_POC_RESET_MASK BIT(7)
21 #define BQ24190_REG_POC_RESET_SHIFT 7
25 #define BQ24190_REG_POC_CHG_CONFIG_MASK GENMASK(5, 4)
40 #define BQ24190_REG_CCC_ICHG_MASK GENMASK(7, 2)
49 /* Pre-charge/Termination Current Cntl */
51 #define BQ24190_REG_PCTCC_IPRECHG_MASK GENMASK(7, 4)
66 #define BQ24190_REG_CVC_VREG_MASK GENMASK(7, 2)
79 #define BQ24190_REG_CTTC_EN_TERM_MASK BIT(7)
80 #define BQ24190_REG_CTTC_EN_TERM_SHIFT 7
83 #define BQ24190_REG_CTTC_WATCHDOG_MASK GENMASK(5, 4)
94 #define BQ24190_REG_ICTRC_BAT_COMP_MASK GENMASK(7, 5)
95 #define BQ24190_REG_ICTRC_BAT_COMP_SHIFT 5
103 #define BQ24190_REG_MOC_DPDM_EN_MASK BIT(7)
104 #define BQ24190_REG_MOC_DPDM_EN_SHIFT 7
107 #define BQ24190_REG_MOC_BATFET_DISABLE_MASK BIT(5)
108 #define BQ24190_REG_MOC_BATFET_DISABLE_SHIFT 5
116 #define BQ24190_REG_SS_VBUS_STAT_MASK GENMASK(7, 6)
118 #define BQ24190_REG_SS_CHRG_STAT_MASK GENMASK(5, 4)
135 #define BQ24190_REG_F_WATCHDOG_FAULT_MASK BIT(7)
136 #define BQ24190_REG_F_WATCHDOG_FAULT_SHIFT 7
139 #define BQ24190_REG_F_CHRG_FAULT_MASK GENMASK(5, 4)
157 #define BQ24190_REG_VPRS_PN_MASK GENMASK(5, 3)