Lines Matching refs:stm32h7_cfg
47 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_read_reg() local
49 return can_mcan_sys_read_reg(stm32h7_cfg->base, reg, val); in can_stm32h7_read_reg()
55 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_write_reg() local
57 return can_mcan_sys_write_reg(stm32h7_cfg->base, reg, val); in can_stm32h7_write_reg()
63 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_read_mram() local
65 return can_mcan_sys_read_mram(stm32h7_cfg->mram, offset, dst, len); in can_stm32h7_read_mram()
72 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_write_mram() local
74 return can_mcan_sys_write_mram(stm32h7_cfg->mram, offset, src, len); in can_stm32h7_write_mram()
80 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_clear_mram() local
82 return can_mcan_sys_clear_mram(stm32h7_cfg->mram, offset, len); in can_stm32h7_clear_mram()
110 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_clock_enable() local
120 if (IS_ENABLED(STM32H7_FDCAN_DOMAIN_CLOCK_SUPPORT) && (stm32h7_cfg->pclk_len > 1)) { in can_stm32h7_clock_enable()
122 (clock_control_subsys_t)&stm32h7_cfg->pclken[1], in can_stm32h7_clock_enable()
135 (clock_control_subsys_t)&stm32h7_cfg->pclken[1], &fdcan_clock); in can_stm32h7_clock_enable()
148 ret = clock_control_on(clk, (clock_control_subsys_t)&stm32h7_cfg->pclken[0]); in can_stm32h7_clock_enable()
154 if (stm32h7_cfg->clock_divider != 0U) { in can_stm32h7_clock_enable()
158 FIELD_PREP(FDCANCCU_CCFG_CDIV, stm32h7_cfg->clock_divider >> 1U); in can_stm32h7_clock_enable()
167 const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom; in can_stm32h7_init() local
171 ret = pinctrl_apply_state(stm32h7_cfg->pcfg, PINCTRL_STATE_DEFAULT); in can_stm32h7_init()
182 ret = can_mcan_configure_mram(dev, stm32h7_cfg->mrba, stm32h7_cfg->mram); in can_stm32h7_init()
192 stm32h7_cfg->config_irq(); in can_stm32h7_init()