5  * SPDX-License-Identifier: Apache-2.0
33  * - TEST register SVAL, TXBNS, PVAL, and TXBNP bits are not available.
34  * - CCCR register VMM and UTSU bits are not available.
35  * - TXBC register TFQS, NDTB, and TBSA fields are not available.
128 /* Tx Buffer Configuration register */
131 /* Tx Buffer Request Pending register */
134 /* Tx Buffer Add Request register */
137 /* Tx Buffer Cancellation Request register */
140 /* Tx Buffer Transmission Occurred register */
143 /* Tx Buffer Cancellation Finished register */
146 /* Tx Buffer Transmission Interrupt Enable register */
149 /* Tx Buffer Cancellation Finished Interrupt Enable register */
152 /* Tx Event FIFO Status register */
155 /* Tx Event FIFO Acknowledge register */
259 	const struct can_mcan_config *mcan_config = dev->config;  in can_stm32fd_read_reg()
260 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;  in can_stm32fd_read_reg()
267 		return -ENOTSUP;  in can_stm32fd_read_reg()
270 	err = can_mcan_sys_read_reg(stm32fd_config->base, remap, &bits);  in can_stm32fd_read_reg()
282 		/* Group 1 map bits 23-16 (stm32fd) to 29-22 (mcan) */  in can_stm32fd_read_reg()
285 		/* Group 2 map bits 15-11 (stm32fd) to 18-14 (mcan) */  in can_stm32fd_read_reg()
288 		/* Group 3 map bits 10-4 (stm32fd) to 12-6 (mcan) */  in can_stm32fd_read_reg()
291 		/* Group 4 map bits 3-1 (stm32fd) to 4-2 (mcan) */  in can_stm32fd_read_reg()
323 	const struct can_mcan_config *mcan_config = dev->config;  in can_stm32fd_write_reg()
324 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;  in can_stm32fd_write_reg()
330 		return -ENOTSUP;  in can_stm32fd_write_reg()
338 		/* Group 1 map bits 29-22 (mcan) to 23-16 (stm32fd) */  in can_stm32fd_write_reg()
341 		/* Group 2 map bits 18-14 (mcan) to 15-11 (stm32fd) */  in can_stm32fd_write_reg()
344 		/* Group 3 map bits 12-6 (mcan) to 10-4 (stm32fd) */  in can_stm32fd_write_reg()
347 		/* Group 4 map bits 4-2 (mcan) to 3-1 (stm32fd) */  in can_stm32fd_write_reg()
376 	return can_mcan_sys_write_reg(stm32fd_config->base, remap, bits);  in can_stm32fd_write_reg()
381 	const struct can_mcan_config *mcan_config = dev->config;  in can_stm32fd_read_mram()
382 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;  in can_stm32fd_read_mram()
384 	return can_mcan_sys_read_mram(stm32fd_config->mram, offset, dst, len);  in can_stm32fd_read_mram()
390 	const struct can_mcan_config *mcan_config = dev->config;  in can_stm32fd_write_mram()
391 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;  in can_stm32fd_write_mram()
393 	return can_mcan_sys_write_mram(stm32fd_config->mram, offset, src, len);  in can_stm32fd_write_mram()
398 	const struct can_mcan_config *mcan_config = dev->config;  in can_stm32fd_clear_mram()
399 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;  in can_stm32fd_clear_mram()
401 	return can_mcan_sys_clear_mram(stm32fd_config->mram, offset, len);  in can_stm32fd_clear_mram()
412 		return -EIO;  in can_stm32fd_get_core_clock()
415 	if (FDCAN_CONFIG->CKDIV == 0) {  in can_stm32fd_get_core_clock()
418 		*rate = rate_tmp / (FDCAN_CONFIG->CKDIV << 1);  in can_stm32fd_get_core_clock()
427 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32fd_clock_enable()
428 	const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;  in can_stm32fd_clock_enable()
432 		return -ENODEV;  in can_stm32fd_clock_enable()
435 	if (IS_ENABLED(STM32_CANFD_DOMAIN_CLOCK_SUPPORT) && (stm32fd_cfg->pclk_len > 1)) {  in can_stm32fd_clock_enable()
437 				(clock_control_subsys_t)&stm32fd_cfg->pclken[1],  in can_stm32fd_clock_enable()
445 	ret = clock_control_on(clk, (clock_control_subsys_t)&stm32fd_cfg->pclken[0]);  in can_stm32fd_clock_enable()
450 	if (stm32fd_cfg->clock_divider != 0) {  in can_stm32fd_clock_enable()
452 		FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1;  in can_stm32fd_clock_enable()
460 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_stm32fd_init()
461 	const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;  in can_stm32fd_init()
466 	ret = pinctrl_apply_state(stm32fd_cfg->pcfg, PINCTRL_STATE_DEFAULT);  in can_stm32fd_init()
494 	/* Setup STM32 FDCAN Tx buffer configuration register */  in can_stm32fd_init()
505 	stm32fd_cfg->config_irq();  in can_stm32fd_init()
545 		     "Standard filter elements must be 28");			\
547 		     "Extended filter elements must be 8");			\
549 		     "Rx FIFO 0 elements must be 3");				\
551 		     "Rx FIFO 1 elements must be 3");				\
553 		     "Rx Buffer elements must be 0");				\
555 		     "Tx Event FIFO elements must be 3");			\
557 		     "Tx Buffer elements must be 0");
576 		     "Insufficient Message RAM size to hold elements");	\