33  * - TEST register SVAL, TXBNS, PVAL, and TXBNP bits are not available.
34  * - CCCR register VMM and UTSU bits are not available.
262 	uint32_t bits;  in can_stm32fd_read_reg()  local
270 	err = can_mcan_sys_read_reg(stm32fd_config->base, remap, &bits);  in can_stm32fd_read_reg()
281 		/* Remap IR/IE bits, ignoring unsupported bits */  in can_stm32fd_read_reg()
282 		/* Group 1 map bits 23-16 (stm32fd) to 29-22 (mcan) */  in can_stm32fd_read_reg()
283 		*val |= ((bits & GENMASK(23, 16)) << 6);  in can_stm32fd_read_reg()
285 		/* Group 2 map bits 15-11 (stm32fd) to 18-14 (mcan) */  in can_stm32fd_read_reg()
286 		*val |= ((bits & GENMASK(15, 11)) << 3);  in can_stm32fd_read_reg()
288 		/* Group 3 map bits 10-4 (stm32fd) to 12-6 (mcan) */  in can_stm32fd_read_reg()
289 		*val |= ((bits & GENMASK(10, 4)) << 2);  in can_stm32fd_read_reg()
291 		/* Group 4 map bits 3-1 (stm32fd) to 4-2 (mcan) */  in can_stm32fd_read_reg()
292 		*val |= ((bits & GENMASK(3, 1)) << 1);  in can_stm32fd_read_reg()
294 		/* Group 5 map bits 0 (mcan) to 0 (stm32fd) */  in can_stm32fd_read_reg()
295 		*val |= ((bits & GENMASK(0, 0)) << 0);  in can_stm32fd_read_reg()
299 		if ((bits & CAN_STM32FD_ILS_RXFIFO1) != 0U) {  in can_stm32fd_read_reg()
303 		if ((bits & CAN_STM32FD_ILS_RXFIFO0) != 0U) {  in can_stm32fd_read_reg()
309 		*val = bits & (CAN_MCAN_GFC_ANFS | CAN_MCAN_GFC_ANFE |  in can_stm32fd_read_reg()
314 		*val = bits;  in can_stm32fd_read_reg()
325 	uint32_t bits = 0U;  in can_stm32fd_write_reg()  local
337 		/* Remap IR/IE bits, ignoring unsupported bits */  in can_stm32fd_write_reg()
338 		/* Group 1 map bits 29-22 (mcan) to 23-16 (stm32fd) */  in can_stm32fd_write_reg()
339 		bits |= ((val & GENMASK(29, 22)) >> 6);  in can_stm32fd_write_reg()
341 		/* Group 2 map bits 18-14 (mcan) to 15-11 (stm32fd) */  in can_stm32fd_write_reg()
342 		bits |= ((val & GENMASK(18, 14)) >> 3);  in can_stm32fd_write_reg()
344 		/* Group 3 map bits 12-6 (mcan) to 10-4 (stm32fd) */  in can_stm32fd_write_reg()
345 		bits |= ((val & GENMASK(12, 6)) >> 2);  in can_stm32fd_write_reg()
347 		/* Group 4 map bits 4-2 (mcan) to 3-1 (stm32fd) */  in can_stm32fd_write_reg()
348 		bits |= ((val & GENMASK(4, 2)) >> 1);  in can_stm32fd_write_reg()
350 		/* Group 5 map bits 0 (mcan) to 0 (stm32fd) */  in can_stm32fd_write_reg()
351 		bits |= ((val & GENMASK(0, 0)) >> 0);  in can_stm32fd_write_reg()
356 			bits |= CAN_STM32FD_ILS_RXFIFO1;  in can_stm32fd_write_reg()
360 			bits |= CAN_STM32FD_ILS_RXFIFO0;  in can_stm32fd_write_reg()
365 		bits |= FIELD_PREP(CAN_STM32FD_RXGFC_LSS, CONFIG_CAN_MAX_STD_ID_FILTER) |  in can_stm32fd_write_reg()
367 		bits |= val & (CAN_MCAN_GFC_ANFS | CAN_MCAN_GFC_ANFE |  in can_stm32fd_write_reg()
372 		bits = val;  in can_stm32fd_write_reg()
376 	return can_mcan_sys_write_reg(stm32fd_config->base, remap, bits);  in can_stm32fd_write_reg()