Lines Matching +full:tx +full:- +full:inst +full:- +full:mode
5 * SPDX-License-Identifier: Apache-2.0
82 can_tx_callback_t callback = mb->tx_callback; in can_stm32_signal_tx_complete()
85 callback(dev, status, mb->callback_arg); in can_stm32_signal_tx_complete()
86 mb->tx_callback = NULL; in can_stm32_signal_tx_complete()
94 if (mbox->RIR & CAN_RI0R_IDE) { in can_stm32_rx_fifo_pop()
95 frame->id = mbox->RIR >> CAN_RI0R_EXID_Pos; in can_stm32_rx_fifo_pop()
96 frame->flags |= CAN_FRAME_IDE; in can_stm32_rx_fifo_pop()
98 frame->id = mbox->RIR >> CAN_RI0R_STID_Pos; in can_stm32_rx_fifo_pop()
101 if ((mbox->RIR & CAN_RI0R_RTR) != 0) { in can_stm32_rx_fifo_pop()
102 frame->flags |= CAN_FRAME_RTR; in can_stm32_rx_fifo_pop()
104 frame->data_32[0] = mbox->RDLR; in can_stm32_rx_fifo_pop()
105 frame->data_32[1] = mbox->RDHR; in can_stm32_rx_fifo_pop()
108 frame->dlc = mbox->RDTR & (CAN_RDT0R_DLC >> CAN_RDT0R_DLC_Pos); in can_stm32_rx_fifo_pop()
110 frame->timestamp = ((mbox->RDTR & CAN_RDT0R_TIME) >> CAN_RDT0R_TIME_Pos); in can_stm32_rx_fifo_pop()
116 struct can_stm32_data *data = dev->data; in can_stm32_rx_isr_handler()
117 const struct can_stm32_config *cfg = dev->config; in can_stm32_rx_isr_handler()
118 CAN_TypeDef *can = cfg->can; in can_stm32_rx_isr_handler()
125 while (can->RF0R & CAN_RF0R_FMP0) { in can_stm32_rx_isr_handler()
126 mbox = &can->sFIFOMailBox[0]; in can_stm32_rx_isr_handler()
127 filter_id = ((mbox->RDTR & CAN_RDT0R_FMI) >> CAN_RDT0R_FMI_Pos); in can_stm32_rx_isr_handler()
134 callback = data->rx_cb_ext[filter_id]; in can_stm32_rx_isr_handler()
135 cb_arg = data->cb_arg_ext[filter_id]; in can_stm32_rx_isr_handler()
137 index = filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER; in can_stm32_rx_isr_handler()
138 callback = data->rx_cb_std[index]; in can_stm32_rx_isr_handler()
139 cb_arg = data->cb_arg_std[index]; in can_stm32_rx_isr_handler()
147 can->RF0R |= CAN_RF0R_RFOM0; in can_stm32_rx_isr_handler()
150 if (can->RF0R & CAN_RF0R_FOVR0) { in can_stm32_rx_isr_handler()
159 const struct can_stm32_config *cfg = dev->config; in can_stm32_get_state()
160 struct can_stm32_data *data = dev->data; in can_stm32_get_state()
161 CAN_TypeDef *can = cfg->can; in can_stm32_get_state()
164 if (!data->common.started) { in can_stm32_get_state()
166 } else if (can->ESR & CAN_ESR_BOFF) { in can_stm32_get_state()
168 } else if (can->ESR & CAN_ESR_EPVF) { in can_stm32_get_state()
170 } else if (can->ESR & CAN_ESR_EWGF) { in can_stm32_get_state()
178 err_cnt->tx_err_cnt = in can_stm32_get_state()
179 ((can->ESR & CAN_ESR_TEC) >> CAN_ESR_TEC_Pos); in can_stm32_get_state()
180 err_cnt->rx_err_cnt = in can_stm32_get_state()
181 ((can->ESR & CAN_ESR_REC) >> CAN_ESR_REC_Pos); in can_stm32_get_state()
189 struct can_stm32_data *data = dev->data; in can_stm32_bus_state_change_isr()
192 const can_state_change_callback_t cb = data->common.state_change_cb; in can_stm32_bus_state_change_isr()
193 void *state_change_cb_data = data->common.state_change_cb_user_data; in can_stm32_bus_state_change_isr()
196 const struct can_stm32_config *cfg = dev->config; in can_stm32_bus_state_change_isr()
197 CAN_TypeDef *can = cfg->can; in can_stm32_bus_state_change_isr()
199 switch (can->ESR & CAN_ESR_LEC) { in can_stm32_bus_state_change_isr()
223 can->ESR |= CAN_ESR_LEC; in can_stm32_bus_state_change_isr()
228 if (state != data->state) { in can_stm32_bus_state_change_isr()
229 data->state = state; in can_stm32_bus_state_change_isr()
239 struct can_stm32_data *data = dev->data; in can_stm32_tx_isr_handler()
240 const struct can_stm32_config *cfg = dev->config; in can_stm32_tx_isr_handler()
241 CAN_TypeDef *can = cfg->can; in can_stm32_tx_isr_handler()
245 bus_off = can->ESR & CAN_ESR_BOFF; in can_stm32_tx_isr_handler()
247 if ((can->TSR & CAN_TSR_RQCP0) | bus_off) { in can_stm32_tx_isr_handler()
248 status = can->TSR & CAN_TSR_TXOK0 ? 0 : in can_stm32_tx_isr_handler()
249 can->TSR & CAN_TSR_TERR0 ? -EIO : in can_stm32_tx_isr_handler()
250 can->TSR & CAN_TSR_ALST0 ? -EBUSY : in can_stm32_tx_isr_handler()
251 bus_off ? -ENETUNREACH : in can_stm32_tx_isr_handler()
252 -EIO; in can_stm32_tx_isr_handler()
254 can->TSR |= CAN_TSR_RQCP0; in can_stm32_tx_isr_handler()
255 can_stm32_signal_tx_complete(dev, &data->mb0, status); in can_stm32_tx_isr_handler()
258 if ((can->TSR & CAN_TSR_RQCP1) | bus_off) { in can_stm32_tx_isr_handler()
259 status = can->TSR & CAN_TSR_TXOK1 ? 0 : in can_stm32_tx_isr_handler()
260 can->TSR & CAN_TSR_TERR1 ? -EIO : in can_stm32_tx_isr_handler()
261 can->TSR & CAN_TSR_ALST1 ? -EBUSY : in can_stm32_tx_isr_handler()
262 bus_off ? -ENETUNREACH : in can_stm32_tx_isr_handler()
263 -EIO; in can_stm32_tx_isr_handler()
265 can->TSR |= CAN_TSR_RQCP1; in can_stm32_tx_isr_handler()
266 can_stm32_signal_tx_complete(dev, &data->mb1, status); in can_stm32_tx_isr_handler()
269 if ((can->TSR & CAN_TSR_RQCP2) | bus_off) { in can_stm32_tx_isr_handler()
270 status = can->TSR & CAN_TSR_TXOK2 ? 0 : in can_stm32_tx_isr_handler()
271 can->TSR & CAN_TSR_TERR2 ? -EIO : in can_stm32_tx_isr_handler()
272 can->TSR & CAN_TSR_ALST2 ? -EBUSY : in can_stm32_tx_isr_handler()
273 bus_off ? -ENETUNREACH : in can_stm32_tx_isr_handler()
274 -EIO; in can_stm32_tx_isr_handler()
276 can->TSR |= CAN_TSR_RQCP2; in can_stm32_tx_isr_handler()
277 can_stm32_signal_tx_complete(dev, &data->mb2, status); in can_stm32_tx_isr_handler()
280 if (can->TSR & CAN_TSR_TME) { in can_stm32_tx_isr_handler()
281 k_sem_give(&data->tx_int_sem); in can_stm32_tx_isr_handler()
289 const struct can_stm32_config *cfg = dev->config; in can_stm32_isr()
290 CAN_TypeDef *can = cfg->can; in can_stm32_isr()
295 if (can->MSR & CAN_MSR_ERRI) { in can_stm32_isr()
297 can->MSR |= CAN_MSR_ERRI; in can_stm32_isr()
315 const struct can_stm32_config *cfg = dev->config; in can_stm32_state_change_isr()
316 CAN_TypeDef *can = cfg->can; in can_stm32_state_change_isr()
318 /* Signal bus-off to waiting tx */ in can_stm32_state_change_isr()
319 if (can->MSR & CAN_MSR_ERRI) { in can_stm32_state_change_isr()
322 can->MSR |= CAN_MSR_ERRI; in can_stm32_state_change_isr()
332 can->MCR |= CAN_MCR_INRQ; in can_stm32_enter_init_mode()
335 while ((can->MSR & CAN_MSR_INAK) == 0U) { in can_stm32_enter_init_mode()
336 if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) { in can_stm32_enter_init_mode()
337 can->MCR &= ~CAN_MCR_INRQ; in can_stm32_enter_init_mode()
338 return -EAGAIN; in can_stm32_enter_init_mode()
349 can->MCR &= ~CAN_MCR_INRQ; in can_stm32_leave_init_mode()
352 while ((can->MSR & CAN_MSR_INAK) != 0U) { in can_stm32_leave_init_mode()
353 if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) { in can_stm32_leave_init_mode()
354 return -EAGAIN; in can_stm32_leave_init_mode()
365 can->MCR &= ~CAN_MCR_SLEEP; in can_stm32_leave_sleep_mode()
368 while ((can->MSR & CAN_MSR_SLAK) != 0) { in can_stm32_leave_sleep_mode()
369 if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) { in can_stm32_leave_sleep_mode()
370 return -EAGAIN; in can_stm32_leave_sleep_mode()
392 const struct can_stm32_config *cfg = dev->config; in can_stm32_start()
393 struct can_stm32_data *data = dev->data; in can_stm32_start()
394 CAN_TypeDef *can = cfg->can; in can_stm32_start()
397 k_mutex_lock(&data->inst_mutex, K_FOREVER); in can_stm32_start()
399 if (data->common.started) { in can_stm32_start()
400 ret = -EALREADY; in can_stm32_start()
404 if (cfg->common.phy != NULL) { in can_stm32_start()
405 ret = can_transceiver_enable(cfg->common.phy, data->common.mode); in can_stm32_start()
416 LOG_ERR("Failed to leave init mode"); in can_stm32_start()
418 if (cfg->common.phy != NULL) { in can_stm32_start()
420 (void)can_transceiver_disable(cfg->common.phy); in can_stm32_start()
423 ret = -EIO; in can_stm32_start()
427 data->common.started = true; in can_stm32_start()
430 k_mutex_unlock(&data->inst_mutex); in can_stm32_start()
437 const struct can_stm32_config *cfg = dev->config; in can_stm32_stop()
438 struct can_stm32_data *data = dev->data; in can_stm32_stop()
439 CAN_TypeDef *can = cfg->can; in can_stm32_stop()
442 k_mutex_lock(&data->inst_mutex, K_FOREVER); in can_stm32_stop()
444 if (!data->common.started) { in can_stm32_stop()
445 ret = -EALREADY; in can_stm32_stop()
451 LOG_ERR("Failed to enter init mode"); in can_stm32_stop()
452 ret = -EIO; in can_stm32_stop()
457 can_stm32_signal_tx_complete(dev, &data->mb0, -ENETDOWN); in can_stm32_stop()
458 can_stm32_signal_tx_complete(dev, &data->mb1, -ENETDOWN); in can_stm32_stop()
459 can_stm32_signal_tx_complete(dev, &data->mb2, -ENETDOWN); in can_stm32_stop()
460 can->TSR |= CAN_TSR_ABRQ2 | CAN_TSR_ABRQ1 | CAN_TSR_ABRQ0; in can_stm32_stop()
462 if (cfg->common.phy != NULL) { in can_stm32_stop()
463 ret = can_transceiver_disable(cfg->common.phy); in can_stm32_stop()
470 data->common.started = false; in can_stm32_stop()
473 k_mutex_unlock(&data->inst_mutex); in can_stm32_stop()
478 static int can_stm32_set_mode(const struct device *dev, can_mode_t mode) in can_stm32_set_mode() argument
481 const struct can_stm32_config *cfg = dev->config; in can_stm32_set_mode()
482 CAN_TypeDef *can = cfg->can; in can_stm32_set_mode()
483 struct can_stm32_data *data = dev->data; in can_stm32_set_mode()
485 LOG_DBG("Set mode %d", mode); in can_stm32_set_mode()
491 if ((mode & ~(supported)) != 0) { in can_stm32_set_mode()
492 LOG_ERR("unsupported mode: 0x%08x", mode); in can_stm32_set_mode()
493 return -ENOTSUP; in can_stm32_set_mode()
496 if (data->common.started) { in can_stm32_set_mode()
497 return -EBUSY; in can_stm32_set_mode()
500 k_mutex_lock(&data->inst_mutex, K_FOREVER); in can_stm32_set_mode()
502 if ((mode & CAN_MODE_LOOPBACK) != 0) { in can_stm32_set_mode()
503 /* Loopback mode */ in can_stm32_set_mode()
504 can->BTR |= CAN_BTR_LBKM; in can_stm32_set_mode()
506 can->BTR &= ~CAN_BTR_LBKM; in can_stm32_set_mode()
509 if ((mode & CAN_MODE_LISTENONLY) != 0) { in can_stm32_set_mode()
510 /* Silent mode */ in can_stm32_set_mode()
511 can->BTR |= CAN_BTR_SILM; in can_stm32_set_mode()
513 can->BTR &= ~CAN_BTR_SILM; in can_stm32_set_mode()
516 if ((mode & CAN_MODE_ONE_SHOT) != 0) { in can_stm32_set_mode()
518 can->MCR |= CAN_MCR_NART; in can_stm32_set_mode()
520 can->MCR &= ~CAN_MCR_NART; in can_stm32_set_mode()
524 if ((mode & CAN_MODE_MANUAL_RECOVERY) != 0) { in can_stm32_set_mode()
525 /* No automatic recovery from bus-off */ in can_stm32_set_mode()
526 can->MCR &= ~CAN_MCR_ABOM; in can_stm32_set_mode()
528 can->MCR |= CAN_MCR_ABOM; in can_stm32_set_mode()
532 data->common.mode = mode; in can_stm32_set_mode()
534 k_mutex_unlock(&data->inst_mutex); in can_stm32_set_mode()
542 const struct can_stm32_config *cfg = dev->config; in can_stm32_set_timing()
543 CAN_TypeDef *can = cfg->can; in can_stm32_set_timing()
544 struct can_stm32_data *data = dev->data; in can_stm32_set_timing()
546 k_mutex_lock(&data->inst_mutex, K_FOREVER); in can_stm32_set_timing()
548 if (data->common.started) { in can_stm32_set_timing()
549 k_mutex_unlock(&data->inst_mutex); in can_stm32_set_timing()
550 return -EBUSY; in can_stm32_set_timing()
553 can->BTR = (can->BTR & ~(CAN_BTR_SJW_Msk | CAN_BTR_BRP_Msk | in can_stm32_set_timing()
555 (((timing->sjw - 1) << CAN_BTR_SJW_Pos) & CAN_BTR_SJW_Msk) | in can_stm32_set_timing()
556 (((timing->phase_seg1 - 1) << CAN_BTR_TS1_Pos) & CAN_BTR_TS1_Msk) | in can_stm32_set_timing()
557 (((timing->phase_seg2 - 1) << CAN_BTR_TS2_Pos) & CAN_BTR_TS2_Msk) | in can_stm32_set_timing()
558 (((timing->prescaler - 1) << CAN_BTR_BRP_Pos) & CAN_BTR_BRP_Msk); in can_stm32_set_timing()
560 k_mutex_unlock(&data->inst_mutex); in can_stm32_set_timing()
567 const struct can_stm32_config *cfg = dev->config; in can_stm32_get_core_clock()
574 (clock_control_subsys_t) &cfg->pclken, in can_stm32_get_core_clock()
578 return -EIO; in can_stm32_get_core_clock()
597 const struct can_stm32_config *cfg = dev->config; in can_stm32_init()
598 struct can_stm32_data *data = dev->data; in can_stm32_init()
599 CAN_TypeDef *can = cfg->can; in can_stm32_init()
606 k_mutex_init(&data->inst_mutex); in can_stm32_init()
607 k_sem_init(&data->tx_int_sem, 0, 1); in can_stm32_init()
609 if (cfg->common.phy != NULL) { in can_stm32_init()
610 if (!device_is_ready(cfg->common.phy)) { in can_stm32_init()
612 return -ENODEV; in can_stm32_init()
619 return -ENODEV; in can_stm32_init()
622 ret = clock_control_on(clock, (clock_control_subsys_t) &cfg->pclken); in can_stm32_init()
625 return -EIO; in can_stm32_init()
629 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in can_stm32_init()
637 LOG_ERR("Failed to enter init mode"); in can_stm32_init()
643 LOG_ERR("Failed to exit sleep mode"); in can_stm32_init()
648 bank_offset = (cfg->can == cfg->master_can) ? 0 : CAN_STM32_NUM_FILTER_BANKS; in can_stm32_init()
649 cfg->master_can->FMR |= CAN_FMR_FINIT; in can_stm32_init()
650 cfg->master_can->FS1R |= ((1U << CONFIG_CAN_MAX_EXT_ID_FILTER) - 1) << bank_offset; in can_stm32_init()
651 cfg->master_can->FMR &= ~CAN_FMR_FINIT; in can_stm32_init()
653 can->MCR &= ~CAN_MCR_TTCM & ~CAN_MCR_ABOM & ~CAN_MCR_AWUM & in can_stm32_init()
656 can->MCR |= CAN_MCR_TTCM; in can_stm32_init()
659 /* Enable automatic bus-off recovery */ in can_stm32_init()
660 can->MCR |= CAN_MCR_ABOM; in can_stm32_init()
662 ret = can_calc_timing(dev, &timing, cfg->common.bitrate, in can_stm32_init()
663 cfg->common.sample_point); in can_stm32_init()
664 if (ret == -EINVAL) { in can_stm32_init()
666 return -EIO; in can_stm32_init()
670 LOG_DBG("Sample-point err : %d", ret); in can_stm32_init()
682 (void)can_stm32_get_state(dev, &data->state, NULL); in can_stm32_init()
684 cfg->config_irq(can); in can_stm32_init()
685 can->IER |= CAN_IER_TMEIE; in can_stm32_init()
694 struct can_stm32_data *data = dev->data; in can_stm32_set_state_change_callback()
695 const struct can_stm32_config *cfg = dev->config; in can_stm32_set_state_change_callback()
696 CAN_TypeDef *can = cfg->can; in can_stm32_set_state_change_callback()
698 data->common.state_change_cb = cb; in can_stm32_set_state_change_callback()
699 data->common.state_change_cb_user_data = user_data; in can_stm32_set_state_change_callback()
702 can->IER &= ~(CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE); in can_stm32_set_state_change_callback()
704 can->IER |= CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE; in can_stm32_set_state_change_callback()
711 const struct can_stm32_config *cfg = dev->config; in can_stm32_recover()
712 struct can_stm32_data *data = dev->data; in can_stm32_recover()
713 CAN_TypeDef *can = cfg->can; in can_stm32_recover()
714 int ret = -EAGAIN; in can_stm32_recover()
717 if (!data->common.started) { in can_stm32_recover()
718 return -ENETDOWN; in can_stm32_recover()
721 if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) { in can_stm32_recover()
722 return -ENOTSUP; in can_stm32_recover()
725 if (!(can->ESR & CAN_ESR_BOFF)) { in can_stm32_recover()
729 if (k_mutex_lock(&data->inst_mutex, K_FOREVER)) { in can_stm32_recover()
730 return -EAGAIN; in can_stm32_recover()
742 while (can->ESR & CAN_ESR_BOFF) { in can_stm32_recover()
744 k_uptime_ticks() - start_time >= timeout.ticks) { in can_stm32_recover()
752 k_mutex_unlock(&data->inst_mutex); in can_stm32_recover()
761 const struct can_stm32_config *cfg = dev->config; in can_stm32_send()
762 struct can_stm32_data *data = dev->data; in can_stm32_send()
763 CAN_TypeDef *can = cfg->can; in can_stm32_send()
772 , frame->dlc, dev->name in can_stm32_send()
773 , frame->id in can_stm32_send()
774 , (frame->flags & CAN_FRAME_IDE) != 0 ? "extended" : "standard" in can_stm32_send()
775 , (frame->flags & CAN_FRAME_RTR) != 0 ? "yes" : "no"); in can_stm32_send()
777 if (frame->dlc > CAN_MAX_DLC) { in can_stm32_send()
778 LOG_ERR("DLC of %d exceeds maximum (%d)", frame->dlc, CAN_MAX_DLC); in can_stm32_send()
779 return -EINVAL; in can_stm32_send()
782 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0) { in can_stm32_send()
783 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags); in can_stm32_send()
784 return -ENOTSUP; in can_stm32_send()
787 if (!data->common.started) { in can_stm32_send()
788 return -ENETDOWN; in can_stm32_send()
791 if (can->ESR & CAN_ESR_BOFF) { in can_stm32_send()
792 return -ENETUNREACH; in can_stm32_send()
795 k_mutex_lock(&data->inst_mutex, K_FOREVER); in can_stm32_send()
796 transmit_status_register = can->TSR; in can_stm32_send()
798 k_mutex_unlock(&data->inst_mutex); in can_stm32_send()
800 if (k_sem_take(&data->tx_int_sem, timeout)) { in can_stm32_send()
801 return -EAGAIN; in can_stm32_send()
804 k_mutex_lock(&data->inst_mutex, K_FOREVER); in can_stm32_send()
805 transmit_status_register = can->TSR; in can_stm32_send()
809 LOG_DBG("Using TX mailbox 0"); in can_stm32_send()
810 mailbox = &can->sTxMailBox[0]; in can_stm32_send()
811 mb = &(data->mb0); in can_stm32_send()
813 LOG_DBG("Using TX mailbox 1"); in can_stm32_send()
814 mailbox = &can->sTxMailBox[1]; in can_stm32_send()
815 mb = &data->mb1; in can_stm32_send()
817 LOG_DBG("Using TX mailbox 2"); in can_stm32_send()
818 mailbox = &can->sTxMailBox[2]; in can_stm32_send()
819 mb = &data->mb2; in can_stm32_send()
822 mb->tx_callback = callback; in can_stm32_send()
823 mb->callback_arg = user_data; in can_stm32_send()
826 mailbox->TIR &= CAN_TI0R_TXRQ; in can_stm32_send()
828 if ((frame->flags & CAN_FRAME_IDE) != 0) { in can_stm32_send()
829 mailbox->TIR |= (frame->id << CAN_TI0R_EXID_Pos) in can_stm32_send()
832 mailbox->TIR |= (frame->id << CAN_TI0R_STID_Pos); in can_stm32_send()
835 if ((frame->flags & CAN_FRAME_RTR) != 0) { in can_stm32_send()
836 mailbox->TIR |= CAN_TI1R_RTR; in can_stm32_send()
838 mailbox->TDLR = frame->data_32[0]; in can_stm32_send()
839 mailbox->TDHR = frame->data_32[1]; in can_stm32_send()
842 mailbox->TDTR = (mailbox->TDTR & ~CAN_TDT1R_DLC) | in can_stm32_send()
843 ((frame->dlc & 0xF) << CAN_TDT1R_DLC_Pos); in can_stm32_send()
845 mailbox->TIR |= CAN_TI0R_TXRQ; in can_stm32_send()
846 k_mutex_unlock(&data->inst_mutex); in can_stm32_send()
855 filter_reg->FR1 = id; in can_stm32_set_filter_bank()
856 filter_reg->FR2 = mask; in can_stm32_set_filter_bank()
858 if ((filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER) % 2 == 0) { in can_stm32_set_filter_bank()
860 filter_reg->FR1 = id | (mask << 16); in can_stm32_set_filter_bank()
863 filter_reg->FR2 = id | (mask << 16); in can_stm32_set_filter_bank()
872 return (filter->mask << CAN_STM32_FIRX_STD_ID_POS) | in can_stm32_filter_to_std_mask()
881 return (filter->mask << CAN_STM32_FIRX_EXT_EXT_ID_POS) | in can_stm32_filter_to_ext_mask()
888 return (filter->id << CAN_STM32_FIRX_STD_ID_POS); in can_stm32_filter_to_std_id()
893 return (filter->id << CAN_STM32_FIRX_EXT_EXT_ID_POS) | in can_stm32_filter_to_ext_id()
899 const struct can_stm32_config *cfg = dev->config; in can_stm32_set_filter()
900 struct can_stm32_data *data = dev->data; in can_stm32_set_filter()
901 CAN_TypeDef *can = cfg->master_can; in can_stm32_set_filter()
904 int filter_id = -ENOSPC; in can_stm32_set_filter()
908 if (cfg->can != cfg->master_can) { in can_stm32_set_filter()
913 if ((filter->flags & CAN_FILTER_IDE) != 0) { in can_stm32_set_filter()
915 if (data->rx_cb_ext[i] == NULL) { in can_stm32_set_filter()
925 if (data->rx_cb_std[i] == NULL) { in can_stm32_set_filter()
935 if (filter_id != -ENOSPC) { in can_stm32_set_filter()
937 filter_id, filter->id, filter->mask); in can_stm32_set_filter()
939 /* set the filter init mode */ in can_stm32_set_filter()
940 can->FMR |= CAN_FMR_FINIT; in can_stm32_set_filter()
942 can_stm32_set_filter_bank(filter_id, &can->sFilterRegister[bank_num], in can_stm32_set_filter()
943 (filter->flags & CAN_FILTER_IDE) != 0, in can_stm32_set_filter()
946 can->FA1R |= 1U << bank_num; in can_stm32_set_filter()
947 can->FMR &= ~(CAN_FMR_FINIT); in can_stm32_set_filter()
957 * This driver uses masked mode for all filters (CAN_FM1R left at reset value
963 * The more complicated list mode must be implemented if someone requires more
971 struct can_stm32_data *data = dev->data; in can_stm32_add_rx_filter()
974 if ((filter->flags & ~(CAN_FILTER_IDE)) != 0) { in can_stm32_add_rx_filter()
975 LOG_ERR("unsupported CAN filter flags 0x%02x", filter->flags); in can_stm32_add_rx_filter()
976 return -ENOTSUP; in can_stm32_add_rx_filter()
980 k_mutex_lock(&data->inst_mutex, K_FOREVER); in can_stm32_add_rx_filter()
984 if ((filter->flags & CAN_FILTER_IDE) != 0) { in can_stm32_add_rx_filter()
985 data->rx_cb_ext[filter_id] = cb; in can_stm32_add_rx_filter()
986 data->cb_arg_ext[filter_id] = cb_arg; in can_stm32_add_rx_filter()
988 data->rx_cb_std[filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER] = cb; in can_stm32_add_rx_filter()
989 data->cb_arg_std[filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER] = cb_arg; in can_stm32_add_rx_filter()
993 k_mutex_unlock(&data->inst_mutex); in can_stm32_add_rx_filter()
1001 const struct can_stm32_config *cfg = dev->config; in can_stm32_remove_rx_filter()
1002 struct can_stm32_data *data = dev->data; in can_stm32_remove_rx_filter()
1003 CAN_TypeDef *can = cfg->master_can; in can_stm32_remove_rx_filter()
1015 k_mutex_lock(&data->inst_mutex, K_FOREVER); in can_stm32_remove_rx_filter()
1017 if (cfg->can != cfg->master_can) { in can_stm32_remove_rx_filter()
1025 data->rx_cb_ext[filter_id] = NULL; in can_stm32_remove_rx_filter()
1026 data->cb_arg_ext[filter_id] = NULL; in can_stm32_remove_rx_filter()
1030 int filter_index = filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER; in can_stm32_remove_rx_filter()
1034 (filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER) / 2; in can_stm32_remove_rx_filter()
1036 data->rx_cb_std[filter_index] = NULL; in can_stm32_remove_rx_filter()
1037 data->cb_arg_std[filter_index] = NULL; in can_stm32_remove_rx_filter()
1040 bank_unused = data->rx_cb_std[filter_index - 1] == NULL; in can_stm32_remove_rx_filter()
1042 bank_unused = data->rx_cb_std[filter_index + 1] == NULL; in can_stm32_remove_rx_filter()
1050 can->FMR |= CAN_FMR_FINIT; in can_stm32_remove_rx_filter()
1052 can_stm32_set_filter_bank(filter_id, &can->sFilterRegister[bank_num], in can_stm32_remove_rx_filter()
1056 can->FA1R &= ~(1U << bank_num); in can_stm32_remove_rx_filter()
1057 LOG_DBG("Filter bank %d is unused -> deactivate", bank_num); in can_stm32_remove_rx_filter()
1060 can->FMR &= ~(CAN_FMR_FINIT); in can_stm32_remove_rx_filter()
1062 k_mutex_unlock(&data->inst_mutex); in can_stm32_remove_rx_filter()
1099 #define CAN_STM32_IRQ_INST(inst) \ argument
1100 static void config_can_##inst##_irq(CAN_TypeDef *can) \
1102 IRQ_CONNECT(DT_INST_IRQN(inst), \
1103 DT_INST_IRQ(inst, priority), \
1104 can_stm32_isr, DEVICE_DT_INST_GET(inst), 0); \
1105 irq_enable(DT_INST_IRQN(inst)); \
1106 can->IER |= CAN_IER_TMEIE | CAN_IER_ERRIE | CAN_IER_FMPIE0 | \
1109 can->IER |= CAN_IER_LECIE; \
1113 #define CAN_STM32_IRQ_INST(inst) \ argument
1114 static void config_can_##inst##_irq(CAN_TypeDef *can) \
1116 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, rx0, irq), \
1117 DT_INST_IRQ_BY_NAME(inst, rx0, priority), \
1118 can_stm32_rx_isr, DEVICE_DT_INST_GET(inst), 0); \
1119 irq_enable(DT_INST_IRQ_BY_NAME(inst, rx0, irq)); \
1120 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, tx, irq), \
1121 DT_INST_IRQ_BY_NAME(inst, tx, priority), \
1122 can_stm32_tx_isr, DEVICE_DT_INST_GET(inst), 0); \
1123 irq_enable(DT_INST_IRQ_BY_NAME(inst, tx, irq)); \
1124 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, sce, irq), \
1125 DT_INST_IRQ_BY_NAME(inst, sce, priority), \
1127 DEVICE_DT_INST_GET(inst), 0); \
1128 irq_enable(DT_INST_IRQ_BY_NAME(inst, sce, irq)); \
1129 can->IER |= CAN_IER_TMEIE | CAN_IER_ERRIE | CAN_IER_FMPIE0 | \
1132 can->IER |= CAN_IER_LECIE; \
1137 #define CAN_STM32_CONFIG_INST(inst) \ argument
1138 PINCTRL_DT_INST_DEFINE(inst); \
1139 static const struct can_stm32_config can_stm32_cfg_##inst = { \
1140 .common = CAN_DT_DRIVER_CONFIG_INST_GET(inst, 0, 1000000), \
1141 .can = (CAN_TypeDef *)DT_INST_REG_ADDR(inst), \
1142 .master_can = (CAN_TypeDef *)DT_INST_PROP_OR(inst, \
1143 master_can_reg, DT_INST_REG_ADDR(inst)), \
1145 .enr = DT_INST_CLOCKS_CELL(inst, bits), \
1146 .bus = DT_INST_CLOCKS_CELL(inst, bus), \
1148 .config_irq = config_can_##inst##_irq, \
1149 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
1152 #define CAN_STM32_DATA_INST(inst) \ argument
1153 static struct can_stm32_data can_stm32_dev_data_##inst;
1155 #define CAN_STM32_DEFINE_INST(inst) \ argument
1156 CAN_DEVICE_DT_INST_DEFINE(inst, can_stm32_init, NULL, \
1157 &can_stm32_dev_data_##inst, &can_stm32_cfg_##inst, \
1161 #define CAN_STM32_INST(inst) \ argument
1162 CAN_STM32_IRQ_INST(inst) \
1163 CAN_STM32_CONFIG_INST(inst) \
1164 CAN_STM32_DATA_INST(inst) \
1165 CAN_STM32_DEFINE_INST(inst)