4  * SPDX-License-Identifier: Apache-2.0
14  *	0: no-cache
19  *	bit[22]: 23th 32KB from 0x000a_8000 to 0x000a_ffff
20  *	bit[23]: 24th 32KB from 0x000b_0000 to 0x000b_ffff
28 #define CACHED_SRAM_END		(CACHED_SRAM_ADDR + CACHED_SRAM_SIZE - 1)
55 	/* set all cache areas to no-cache by default */  in aspeed_cache_init()
59 	max_bit = 8 * sizeof(uint32_t) - 1;  in aspeed_cache_init()
70  * @param [IN] addr - start address to be invalidated
71  * @param [IN] size - size in byte
72  * @param [OUT] p_aligned_addr - pointer to the cacheline aligned address variable
76  *   |--------size-------------|
77  * |-----|-----|-----|-----|-----|
93 	uint32_t n = 0;  in get_n_cacheline()  local
100 	tail = addr + size + (CACHE_LINE_SIZE - 1);  in get_n_cacheline()
103 	n = (tail - *p_head) >> CACHE_LINE_SIZE_LOG2;  in get_n_cacheline()
105 	return n;  in get_n_cacheline()
163 	uint32_t aligned_addr, i, n;  in cache_data_invd_range()  local
177 	n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);  in cache_data_invd_range()
179 	for (i = 0; i < n; i++) {  in cache_data_invd_range()
224 	uint32_t aligned_addr, i, n;  in cache_instr_invd_range()  local
233 	n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);  in cache_instr_invd_range()
240 	for (i = 0; i < n; i++) {  in cache_instr_invd_range()
257 	return -ENOTSUP;  in cache_data_flush_all()
262 	return -ENOTSUP;  in cache_data_flush_and_invd_all()
270 	return -ENOTSUP;  in cache_data_flush_range()
278 	return -ENOTSUP;  in cache_data_flush_and_invd_range()
283 	return -ENOTSUP;  in cache_instr_flush_all()
288 	return -ENOTSUP;  in cache_instr_flush_and_invd_all()
296 	return -ENOTSUP;  in cache_instr_flush_range()
304 	return -ENOTSUP;  in cache_instr_flush_and_invd_range()