Lines Matching refs:K_CACHE_WB
54 #define K_CACHE_WB BIT(0) macro
56 #define K_CACHE_WB_INVD (K_CACHE_WB | K_CACHE_INVD)
153 case K_CACHE_WB: in nds_l1d_cache_all()
186 case K_CACHE_WB: in nds_l1d_cache_range()
295 ret |= nds_l2_cache_all(K_CACHE_WB); in cache_data_invd_all()
298 ret |= nds_l1d_cache_all(K_CACHE_WB); in cache_data_invd_all()
299 ret |= nds_l2_cache_all(K_CACHE_WB); in cache_data_invd_all()
397 ret |= nds_l2_cache_all(K_CACHE_WB); in cache_data_flush_all()
399 ret |= nds_l1d_cache_all(K_CACHE_WB); in cache_data_flush_all()
400 ret |= nds_l2_cache_all(K_CACHE_WB); in cache_data_flush_all()
417 ret |= nds_l2_cache_range(addr, size, K_CACHE_WB); in cache_data_flush_range()
419 ret |= nds_l1d_cache_range(addr, size, K_CACHE_WB); in cache_data_flush_range()
420 ret |= nds_l2_cache_range(addr, size, K_CACHE_WB); in cache_data_flush_range()
440 ret |= nds_l1d_cache_all(K_CACHE_WB); in cache_data_flush_and_invd_all()
465 ret |= nds_l1d_cache_range(addr, size, K_CACHE_WB); in cache_data_flush_and_invd_range()