Lines Matching refs:BIT
18 #define MODE_CTRL_RESET BIT(7)
19 #define MODE_CTRL_RESET_MASK BIT(7)
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
29 #define MISC_CTRL_1_HPF_BYPASS BIT(7)
30 #define MISC_CTRL_1_HPF_BYPASS_MASK BIT(7)
37 #define MISC_CTRL_1_OC_CONTROL BIT(4)
38 #define MISC_CTRL_1_OC_CONTROL_MASK BIT(4)
61 #define MISC_CTRL_2_SDM_OSR BIT(2)
62 #define MISC_CTRL_2_SDM_OSR_MASK BIT(2)
76 #define SAP_CTRL_TDM_SLOT_SELECT BIT(5)
77 #define SAP_CTRL_TDM_SLOT_SELECT_MASK BIT(5)
78 #define SAP_CTRL_TDM_SLOT_SIZE BIT(4)
79 #define SAP_CTRL_TDM_SLOT_SIZE_MASK BIT(4)
80 #define SAP_CTRL_TDM_SLOT_SELECT_2 BIT(3)
81 #define SAP_CTRL_TDM_SLOT_SELECT_2_MASK BIT(3)
111 #define DC_LDG_CTRL_1_ABORT BIT(7)
112 #define DC_LDG_CTRL_1_ABORT_MASK BIT(7)
113 #define DC_LDG_CTRL_1_DOUBLE_RAMP BIT(6)
114 #define DC_LDG_CTRL_1_DOUBLE_RAMP_MASK BIT(6)
115 #define DC_LDG_CTRL_1_DOUBLE_SETTLE BIT(5)
116 #define DC_LDG_CTRL_1_DOUBLE_SETTLE_MASK BIT(5)
117 #define DC_LDG_CTRL_1_LO_ENABLE BIT(1)
118 #define DC_LDG_CTRL_1_LO_ENABLE_MASK BIT(1)
119 #define DC_LDG_CTRL_1_BYPASS BIT(0)
120 #define DC_LDG_CTRL_1_BYPASS_MASK BIT(0)
131 #define DC_LDG_REPORT_1_CH1_S2G BIT(7)
132 #define DC_LDG_REPORT_1_CH1_S2G_MASK BIT(7)
133 #define DC_LDG_REPORT_1_CH1_S2P BIT(6)
134 #define DC_LDG_REPORT_1_CH1_S2P_MASK BIT(6)
135 #define DC_LDG_REPORT_1_CH1_OL BIT(5)
136 #define DC_LDG_REPORT_1_CH1_OL_MASK BIT(5)
137 #define DC_LDG_REPORT_1_CH1_SL BIT(4)
138 #define DC_LDG_REPORT_1_CH1_SL_MASK BIT(4)
139 #define DC_LDG_REPORT_1_CH2_S2G BIT(3)
140 #define DC_LDG_REPORT_1_CH2_S2G_MASK BIT(3)
141 #define DC_LDG_REPORT_1_CH2_S2P BIT(2)
142 #define DC_LDG_REPORT_1_CH2_S2P_MASK BIT(2)
143 #define DC_LDG_REPORT_1_CH2_OL BIT(1)
144 #define DC_LDG_REPORT_1_CH2_OL_MASK BIT(1)
145 #define DC_LDG_REPORT_1_CH2_SL BIT(0)
146 #define DC_LDG_REPORT_1_CH2_SL_MASK BIT(0)
150 #define DC_LDG_REPORT_3_CH1_LO BIT(3)
151 #define DC_LDG_REPORT_3_CH1_LO_MASK BIT(3)
152 #define DC_LDG_REPORT_3_CH2_LO BIT(2)
153 #define DC_LDG_REPORT_3_CH2_LO_MASK BIT(2)
157 #define CH_FAULTS_CH1_OC BIT(7)
158 #define CH_FAULTS_CH1_OC_MASK BIT(7)
159 #define CH_FAULTS_CH2_OC BIT(6)
160 #define CH_FAULTS_CH2_OC_MASK BIT(6)
161 #define CH_FAULTS_CH1_DC BIT(3)
162 #define CH_FAULTS_CH1_DC_MASK BIT(3)
163 #define CH_FAULTS_CH2_DC BIT(2)
164 #define CH_FAULTS_CH2_DC_MASK BIT(2)
168 #define GLOBAL_FAULTS_1_INVALID_CLOCK BIT(4)
169 #define GLOBAL_FAULTS_1_INVALID_CLOCK_MASK BIT(4)
170 #define GLOBAL_FAULTS_1_PVDD_OV BIT(3)
171 #define GLOBAL_FAULTS_1_PVDD_OV_MASK BIT(3)
172 #define GLOBAL_FAULTS_1_VBAT_OV BIT(2)
173 #define GLOBAL_FAULTS_1_VBAT_OV_MASK BIT(2)
174 #define GLOBAL_FAULTS_1_PVDD_UV BIT(1)
175 #define GLOBAL_FAULTS_1_PVDD_UV_MASK BIT(1)
176 #define GLOBAL_FAULTS_1_VBAT_UV BIT(0)
177 #define GLOBAL_FAULTS_1_VBAT_UV_MASK BIT(0)
181 #define GLOBAL_FAULTS_2_OTSD BIT(4)
182 #define GLOBAL_FAULTS_2_OTSD_MASK BIT(4)
183 #define GLOBAL_FAULTS_2_CH1_OTSD BIT(3)
184 #define GLOBAL_FAULTS_2_CH1_OTSD_MASK BIT(3)
185 #define GLOBAL_FAULTS_2_CH2_OTSD BIT(2)
186 #define GLOBAL_FAULTS_2_CH2_OTSD_MASK BIT(2)
190 #define WARNINGS_VDD_POR BIT(5)
191 #define WARNINGS_VDD_POR_MASK BIT(5)
192 #define WARNINGS_OTW BIT(4)
193 #define WARNINGS_OTW_MASK BIT(4)
194 #define WARNINGS_OTW_CH1 BIT(3)
195 #define WARNINGS_OTW_CH1_MASK BIT(3)
196 #define WARNINGS_OTW_CH2 BIT(2)
197 #define WARNINGS_OTW_CH2_MASK BIT(2)
201 #define PIN_CTRL_MASK_OC BIT(7)
202 #define PIN_CTRL_MASK_OC_MASK BIT(7)
203 #define PIN_CTRL_MASK_OTSD BIT(6)
204 #define PIN_CTRL_MASK_OTSD_MASK BIT(6)
205 #define PIN_CTRL_MASK_UV BIT(5)
206 #define PIN_CTRL_MASK_UV_MASK BIT(5)
207 #define PIN_CTRL_MASK_OV BIT(4)
208 #define PIN_CTRL_MASK_OV_MASK BIT(4)
209 #define PIN_CTRL_MASK_DC BIT(3)
210 #define PIN_CTRL_MASK_DC_MASK BIT(3)
211 #define PIN_CTRL_MASK_ILIMIT BIT(2)
212 #define PIN_CTRL_MASK_ILIMIT_MASK BIT(2)
213 #define PIN_CTRL_MASK_CLIP BIT(1)
214 #define PIN_CTRL_MASK_CLIP_MASK BIT(1)
215 #define PIN_CTRL_MASK_OTW BIT(0)
216 #define PIN_CTRL_MASK_OTW_MASK BIT(0)
220 #define MISC_CTRL_3_CLEAR_FAULT BIT(7)
221 #define MISC_CTRL_3_CLEAR_FAULT_MASK BIT(7)
222 #define MISC_CTRL_3_PBTL_CH_SEL BIT(6)
223 #define MISC_CTRL_3_PBTL_CH_SEL_MASK BIT(6)
224 #define MISC_CTRL_3_MASK_ILIMIT BIT(5)
225 #define MISC_CTRL_3_MASK_ILIMIT_MASK BIT(5)
226 #define MISC_CTRL_3_OTSD_AUTO_RECOVERY BIT(3)
227 #define MISC_CTRL_3_OTSD_AUTO_RECOVERY_MASK BIT(3)
231 #define ILIMIT_STATUS_CH2_ILIMIT_WARN BIT(1)
232 #define ILIMIT_STATUS_CH2_ILIMIT_WARN_MASK BIT(1)
233 #define ILIMIT_STATUS_CH1_ILIMIT_WARN BIT(0)
234 #define ILIMIT_STATUS_CH1_ILIMIT_WARN_MASK BIT(0)
251 #define MISC_CTRL_5_SS_BW_SEL BIT(7)
252 #define MISC_CTRL_5_SS_BW_SEL_MASK BIT(7)
253 #define MISC_CTRL_5_SS_DIV2 BIT(6)
254 #define MISC_CTRL_5_SS_DIV2_MASK BIT(6)
255 #define MISC_CTRL_5_PHASE_SEL_MSB BIT(5)
256 #define MISC_CTRL_5_PHASE_SEL_MSB_MASK BIT(5)