Lines Matching +full:5 +full:- +full:7
4 * SPDX-License-Identifier: Apache-2.0
18 #define MODE_CTRL_RESET BIT(7)
19 #define MODE_CTRL_RESET_MASK BIT(7)
29 #define MISC_CTRL_1_HPF_BYPASS BIT(7)
30 #define MISC_CTRL_1_HPF_BYPASS_MASK BIT(7)
31 #define MISC_CTRL_1_OTW_CONTROL_MASK (BIT_MASK(2) << 5)
32 #define MISC_CTRL_1_OTW_CONTROL(val) (((val) << 5) & MISC_CTRL_1_OTW_CONTROL_MASK)
58 #define MISC_CTRL_2_PWM_FREQUENCY_38_FS 5
60 #define MISC_CTRL_2_PWM_FREQUENCY_48_FS 7
69 /* Serial Audio-Port Control Register */
76 #define SAP_CTRL_TDM_SLOT_SELECT BIT(5)
77 #define SAP_CTRL_TDM_SLOT_SELECT_MASK BIT(5)
89 #define SAP_CTRL_INPUT_FORMAT_LEFT 5
111 #define DC_LDG_CTRL_1_ABORT BIT(7)
112 #define DC_LDG_CTRL_1_ABORT_MASK BIT(7)
115 #define DC_LDG_CTRL_1_DOUBLE_SETTLE BIT(5)
116 #define DC_LDG_CTRL_1_DOUBLE_SETTLE_MASK BIT(5)
131 #define DC_LDG_REPORT_1_CH1_S2G BIT(7)
132 #define DC_LDG_REPORT_1_CH1_S2G_MASK BIT(7)
135 #define DC_LDG_REPORT_1_CH1_OL BIT(5)
136 #define DC_LDG_REPORT_1_CH1_OL_MASK BIT(5)
157 #define CH_FAULTS_CH1_OC BIT(7)
158 #define CH_FAULTS_CH1_OC_MASK BIT(7)
190 #define WARNINGS_VDD_POR BIT(5)
191 #define WARNINGS_VDD_POR_MASK BIT(5)
201 #define PIN_CTRL_MASK_OC BIT(7)
202 #define PIN_CTRL_MASK_OC_MASK BIT(7)
205 #define PIN_CTRL_MASK_UV BIT(5)
206 #define PIN_CTRL_MASK_UV_MASK BIT(5)
220 #define MISC_CTRL_3_CLEAR_FAULT BIT(7)
221 #define MISC_CTRL_3_CLEAR_FAULT_MASK BIT(7)
224 #define MISC_CTRL_3_MASK_ILIMIT BIT(5)
225 #define MISC_CTRL_3_MASK_ILIMIT_MASK BIT(5)
245 #define MISC_CTRL_4_HPF_CORNER_118_HZ 5
247 #define MISC_CTRL_4_HPF_CORNER_463_HZ 7
249 /* Miscellaneous Control 5 Register */
251 #define MISC_CTRL_5_SS_BW_SEL BIT(7)
252 #define MISC_CTRL_5_SS_BW_SEL_MASK BIT(7)
255 #define MISC_CTRL_5_PHASE_SEL_MSB BIT(5)
256 #define MISC_CTRL_5_PHASE_SEL_MSB_MASK BIT(5)