Lines Matching full:3
22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
36 #define MISC_CTRL_1_OTW_CONTROL_110_DEGREE 3
44 #define MISC_CTRL_1_VOLUME_RATE_1_STEP_EVERY_8_FSYNC 3
50 #define MISC_CTRL_1_GAIN_29_V_PEAK_OUTPUT 3
54 #define MISC_CTRL_2_PWM_FREQUENCY_MASK (BIT_MASK(3) << 4)
67 #define MISC_CTRL_2_OUTPUT_PHASE_240_DEGREES 3
80 #define SAP_CTRL_TDM_SLOT_SELECT_2 BIT(3)
81 #define SAP_CTRL_TDM_SLOT_SELECT_2_MASK BIT(3)
82 #define SAP_CTRL_INPUT_FORMAT_MASK BIT_MASK(3)
87 #define SAP_CTRL_INPUT_FORMAT_16_BITS_RIGHT 3
101 #define CH_STATE_CTRL_DC_LOAD 3
139 #define DC_LDG_REPORT_1_CH2_S2G BIT(3)
140 #define DC_LDG_REPORT_1_CH2_S2G_MASK BIT(3)
148 /* DC Load Diagnostics Report 3 */
150 #define DC_LDG_REPORT_3_CH1_LO BIT(3)
151 #define DC_LDG_REPORT_3_CH1_LO_MASK BIT(3)
161 #define CH_FAULTS_CH1_DC BIT(3)
162 #define CH_FAULTS_CH1_DC_MASK BIT(3)
170 #define GLOBAL_FAULTS_1_PVDD_OV BIT(3)
171 #define GLOBAL_FAULTS_1_PVDD_OV_MASK BIT(3)
183 #define GLOBAL_FAULTS_2_CH1_OTSD BIT(3)
184 #define GLOBAL_FAULTS_2_CH1_OTSD_MASK BIT(3)
194 #define WARNINGS_OTW_CH1 BIT(3)
195 #define WARNINGS_OTW_CH1_MASK BIT(3)
209 #define PIN_CTRL_MASK_DC BIT(3)
210 #define PIN_CTRL_MASK_DC_MASK BIT(3)
218 /* Miscellaneous Control 3 Register */
226 #define MISC_CTRL_3_OTSD_AUTO_RECOVERY BIT(3)
227 #define MISC_CTRL_3_OTSD_AUTO_RECOVERY_MASK BIT(3)
238 #define MISC_CTRL_4_HPF_CORNER_MASK BIT_MASK(3)
243 #define MISC_CTRL_4_HPF_CORNER_30_HZ 3