9  * SPDX-License-Identifier: Apache-2.0
46 #include <zephyr/dt-bindings/adc/stm32_adc.h>
51 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
56 #include <zephyr/linker/linker-defs.h>
81  * compat st_stm32f1_adc -> STM32F1, F37x (ADC1_V2_5)
82  * compat st_stm32f4_adc -> STM32F2, F4, F7, L1
196 	/* Allow ADC to create DMA request and set to one-shot mode as implemented in HAL drivers */  in adc_stm32_enable_dma_support()
213 	const struct adc_stm32_cfg *config = dev->config;  in adc_stm32_dma_start()
214 	ADC_TypeDef *adc = config->base;  in adc_stm32_dma_start()
215 	struct adc_stm32_data *data = dev->data;  in adc_stm32_dma_start()
219 	struct stream *dma = &data->dma;  in adc_stm32_dma_start()
221 	blk_cfg = &dma->dma_blk_cfg;  in adc_stm32_dma_start()
224 	blk_cfg->block_size = channel_count * sizeof(int16_t);  in adc_stm32_dma_start()
227 	blk_cfg->source_address = (uint32_t)LL_ADC_DMA_GetRegAddr(adc, LL_ADC_DMA_REG_REGULAR_DATA);  in adc_stm32_dma_start()
228 	blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;  in adc_stm32_dma_start()
229 	blk_cfg->source_reload_en = 0;  in adc_stm32_dma_start()
231 	blk_cfg->dest_address = (uint32_t)buffer;  in adc_stm32_dma_start()
232 	blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;  in adc_stm32_dma_start()
233 	blk_cfg->dest_reload_en = 0;  in adc_stm32_dma_start()
238 	blk_cfg->fifo_mode_control = 0;  in adc_stm32_dma_start()
241 	dma->dma_cfg.head_block = blk_cfg;  in adc_stm32_dma_start()
242 	dma->dma_cfg.user_data = data;  in adc_stm32_dma_start()
244 	ret = dma_config(data->dma.dma_dev, data->dma.channel,  in adc_stm32_dma_start()
245 			 &dma->dma_cfg);  in adc_stm32_dma_start()
253 	data->dma_error = 0;  in adc_stm32_dma_start()
254 	ret = dma_start(data->dma.dma_dev, data->dma.channel);  in adc_stm32_dma_start()
267 /* Returns true if given buffer is in a non-cacheable SRAM region.
272  *		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) | ... )>;
281 		((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end));  in buf_in_nocache()
301 	if (sequence->options) {  in check_buffer()
302 		needed_buffer_size *= (1 + sequence->options->extra_samplings);  in check_buffer()
305 	if (sequence->buffer_size < needed_buffer_size) {  in check_buffer()
307 				sequence->buffer_size, needed_buffer_size);  in check_buffer()
308 		return -ENOMEM;  in check_buffer()
312 	/* Buffer is forced to be in non-cacheable SRAM region to avoid cache maintenance */  in check_buffer()
313 	if (!buf_in_nocache((uintptr_t)sequence->buffer, needed_buffer_size)) {  in check_buffer()
314 		LOG_ERR("Supplied buffer is not in a non-cacheable region according to DTS.");  in check_buffer()
315 		return -EINVAL;  in check_buffer()
353 			return -ETIMEDOUT;  in adc_stm32_enable()
358 	 * On STM32F1, F2, F37x, F4, F7 and L1, do not re-enable the ADC.  in adc_stm32_enable()
370 	const struct adc_stm32_cfg *config = dev->config;  in adc_stm32_start_conversion()
371 	ADC_TypeDef *adc = config->base;  in adc_stm32_start_conversion()
452 	const struct adc_stm32_cfg *config = dev->config;  in adc_stm32_calibration_delay()
457 		(clock_control_subsys_t) &config->pclken[0], &adc_rate) < 0) {  in adc_stm32_calibration_delay()
468 	for (int i = wait_cycles; i >= 0; i--) {  in adc_stm32_calibration_delay()
475 		(const struct adc_stm32_cfg *)dev->config;  in adc_stm32_calibration_start()
476 	ADC_TypeDef *adc = config->base;  in adc_stm32_calibration_start()
509 			MODIFY_REG(adc->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos);  in adc_stm32_calibration_start()
511 			MODIFY_REG(adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL);  in adc_stm32_calibration_start()
513 			SET_BIT(adc->CALFACT, ADC_CALFACT_LATCH_COEF);  in adc_stm32_calibration_start()
531 		(const struct adc_stm32_cfg *)dev->config;  in adc_stm32_calibrate()
532 	ADC_TypeDef *adc = config->base;  in adc_stm32_calibrate()
682  * ratio is directly the sequence->oversampling (a 2^n value)
687 	const struct adc_stm32_cfg *config = dev->config;  in adc_stm32_oversampling()
688 	ADC_TypeDef *adc = config->base;  in adc_stm32_oversampling()
697 		return -EINVAL;  in adc_stm32_oversampling()
703 	if (config->oversampler_type == OVERSAMPLER_MINIMAL) {  in adc_stm32_oversampling()
710 	if (config->oversampler_type == OVERSAMPLER_EXTENDED) {  in adc_stm32_oversampling()
727 	const struct adc_stm32_cfg *config = data->dev->config;  in dma_callback()
728 	ADC_TypeDef *adc = config->base;  in dma_callback()
733 	if (channel == data->dma.channel) {  in dma_callback()
742 			data->samples_count = data->channel_count;  in dma_callback()
743 			data->buffer += data->channel_count;  in dma_callback()
749 			dma_stop(data->dma.dma_dev, data->dma.channel);  in dma_callback()
751 			 * the address is in a non-cacheable SRAM region.  in dma_callback()
753 			adc_context_on_sampling_done(&data->ctx, dev);  in dma_callback()
762 			data->dma_error = status;  in dma_callback()
766 			dma_stop(data->dma.dma_dev, data->dma.channel);  in dma_callback()
767 			adc_context_complete(&data->ctx, status);  in dma_callback()
776 	const struct adc_stm32_cfg *config = dev->config;  in get_reg_value()
777 	ADC_TypeDef *adc = config->base;  in get_reg_value()
787 	const struct adc_stm32_cfg *config = dev->config;  in set_reg_value()
788 	ADC_TypeDef *adc = config->base;  in set_reg_value()
798 	const struct adc_stm32_cfg *config = dev->config;  in set_resolution()
799 	ADC_TypeDef *adc = config->base;  in set_resolution()
806 	for (i = 0; i < config->res_table_size; i++) {  in set_resolution()
807 		if (sequence->resolution == STM32_ADC_GET_REAL_VAL(config->res_table[i])) {  in set_resolution()
808 			res_reg_addr = STM32_ADC_GET_REG(config->res_table[i]);  in set_resolution()
809 			res_shift = STM32_ADC_GET_SHIFT(config->res_table[i]);  in set_resolution()
810 			res_mask = STM32_ADC_GET_MASK(config->res_table[i]);  in set_resolution()
811 			res_reg_val = STM32_ADC_GET_REG_VAL(config->res_table[i]);  in set_resolution()
816 	if (i == config->res_table_size) {  in set_resolution()
818 		return -EINVAL;  in set_resolution()
849 	const struct adc_stm32_cfg *config = dev->config;  in set_sequencer()
850 	struct adc_stm32_data *data = dev->data;  in set_sequencer()
851 	ADC_TypeDef *adc = config->base;  in set_sequencer()
858 	 * - channel_index: ranging from 0 -> ( data->channel_count - 1 )  in set_sequencer()
859 	 * - channel_id: ordinal position of channel in data->channels bitmask  in set_sequencer()
861 	for (uint32_t channels = data->channels; channels;  in set_sequencer()
863 		channel_id = find_lsb_set(channels) - 1;  in set_sequencer()
870 		if (config->sequencer_type == FULLY_CONFIGURABLE) {  in set_sequencer()
885 	if (config->sequencer_type == NOT_FULLY_CONFIGURABLE) {  in set_sequencer()
914 	const struct adc_stm32_cfg *config = dev->config;  in start_read()
915 	struct adc_stm32_data *data = dev->data;  in start_read()
916 	ADC_TypeDef *adc = config->base;  in start_read()
919 	data->buffer = sequence->buffer;  in start_read()
920 	data->channels = sequence->channels;  in start_read()
921 	data->channel_count = POPCOUNT(data->channels);  in start_read()
922 	data->samples_count = 0;  in start_read()
924 	if (data->channel_count == 0) {  in start_read()
926 		return -EINVAL;  in start_read()
930 	if (data->channel_count > ARRAY_SIZE(table_seq_len)) {  in start_read()
932 		return -EINVAL;  in start_read()
938 	if (data->channel_count > 1) {  in start_read()
940 		return -EINVAL;  in start_read()
956 	err = check_buffer(sequence, data->channel_count);  in start_read()
962 	err = adc_stm32_oversampling(dev, sequence->oversampling);  in start_read()
967 	if (sequence->oversampling) {  in start_read()
969 		return -ENOTSUP;  in start_read()
973 	if (sequence->calibrate) {  in start_read()
978 		return -ENOTSUP;  in start_read()
1006 	adc_context_start_read(&data->ctx, sequence);  in start_read()
1008 	int result = adc_context_wait_for_completion(&data->ctx);  in start_read()
1012 	result = (data->dma_error ? data->dma_error : result);  in start_read()
1022 	const struct device *dev = data->dev;  in adc_context_start_sampling()
1023 	const struct adc_stm32_cfg *config = dev->config;  in adc_context_start_sampling()
1024 	ADC_TypeDef *adc = config->base;  in adc_context_start_sampling()
1029 	data->repeat_buffer = data->buffer;  in adc_context_start_sampling()
1036 	adc_stm32_dma_start(dev, data->buffer, data->channel_count);  in adc_context_start_sampling()
1048 		data->buffer = data->repeat_buffer;  in adc_context_update_buffer_pointer()
1055 	struct adc_stm32_data *data = dev->data;
1057 		(const struct adc_stm32_cfg *)dev->config;
1058 	ADC_TypeDef *adc = config->base;
1075 		*data->buffer++ = LL_ADC_REG_ReadConversionData32(adc);
1076 		/* ISR is triggered after each conversion, and at the end-of-sequence. */
1077 		if (++data->samples_count == data->channel_count) {
1078 			data->samples_count = 0;
1079 			adc_context_on_sampling_done(&data->ctx, dev);
1089 	LOG_DBG("%s ISR triggered.", dev->name);
1097 	const struct adc_stm32_cfg *config = data->dev->config;
1098 	ADC_TypeDef *adc = config->base;
1103 	data->acq_time_index[0] = -1;
1104 	data->acq_time_index[1] = -1;
1117 	struct adc_stm32_data *data = dev->data;
1120 	adc_context_lock(&data->ctx, false, NULL);
1126 	adc_context_release(&data->ctx, error);
1136 	struct adc_stm32_data *data = dev->data;
1139 	adc_context_lock(&data->ctx, true, async);
1145 	adc_context_release(&data->ctx, error);
1154 		(const struct adc_stm32_cfg *)dev->config;
1161 		return STM32_NB_SAMPLING_TIME - 1;
1166 					     config->sampling_time_table[i])) {
1172 	return -EINVAL;
1179 		(const struct adc_stm32_cfg *)dev->config;
1180 	ADC_TypeDef *adc = config->base;
1181 	struct adc_stm32_data *data = dev->data;
1196 	switch (config->num_sampling_time_common_channels) {
1210 		if ((data->acq_time_index[0] == -1) ||
1211 			(acq_time_index == data->acq_time_index[0])) {
1213 			data->acq_time_index[0] = acq_time_index;
1219 			return -EINVAL;
1228 		if ((data->acq_time_index[0] == -1) ||
1229 			(acq_time_index == data->acq_time_index[0])) {
1231 			data->acq_time_index[0] = acq_time_index;
1238 		} else if ((data->acq_time_index[1] == -1) ||
1239 			(acq_time_index == data->acq_time_index[1])) {
1241 			data->acq_time_index[1] = acq_time_index;
1251 			return -EINVAL;
1257 		return -EINVAL;
1266 	const struct adc_stm32_cfg *config = (const struct adc_stm32_cfg *)dev->config;
1267 	ADC_TypeDef *adc = config->base;
1270 	if (channel_cfg->differential) {
1272 		return -EINVAL;
1275 	if (channel_cfg->gain != ADC_GAIN_1) {
1277 		return -EINVAL;
1280 	if (channel_cfg->reference != ADC_REF_INTERNAL) {
1282 		return -EINVAL;
1285 	if (adc_stm32_sampling_time_setup(dev, channel_cfg->channel_id,
1286 					  channel_cfg->acquisition_time) != 0) {
1288 		return -EINVAL;
1293 		if (channel_cfg->channel_id == 0) {
1316 	if (config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV1 ||
1317 	    config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV2 ||
1318 	    config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV4) {
1343 	switch (config->clk_prescaler) {
1372 		return -EINVAL;
1385 	clk_src = (clock_control_subsys_t)(adc_stm32_is_clk_sync(config) ? &config->pclken[0]
1386 									 : &config->pclken[1]);
1390 		return -EIO;
1393 	/* Adjust the pre-scaler value so that we can divide down the clock */
1414 		return -ERANGE;
1433 	const struct adc_stm32_cfg *config = dev->config;
1435 	ADC_TypeDef *adc = config->base;
1441 		(clock_control_subsys_t) &config->pclken[0]) != 0) {
1442 		return -EIO;
1445 	if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) {
1448 					    (clock_control_subsys_t) &config->pclken[1],
1450 			return -EIO;
1455 	LL_ADC_SetClock(adc, config->clk_prescaler);
1458 		LL_ADC_SetClock(adc, config->clk_prescaler);
1461 				      config->clk_prescaler);
1466 			      config->clk_prescaler);
1479 	struct adc_stm32_data *data = dev->data;
1480 	const struct adc_stm32_cfg *config = dev->config;
1482 	ADC_TypeDef *adc = config->base;
1487 	LOG_DBG("Initializing %s", dev->name);
1491 		return -ENODEV;
1494 	data->dev = dev;
1505 	data->acq_time_index[0] = -1;
1506 	data->acq_time_index[1] = -1;
1511 	err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1512 	if ((err < 0) && (err != -ENOENT)) {
1515 		 * provided in Device Tree, and pinctrl_apply_state returns -ENOENT,
1528 	if ((data->dma.dma_dev != NULL) &&
1529 	    !device_is_ready(data->dma.dma_dev)) {
1530 		LOG_ERR("%s device not ready", data->dma.dma_dev->name);
1531 		return -ENODEV;
1580 	if (config->irq_cfg_func) {
1581 		config->irq_cfg_func();
1589 	adc_context_unlock_unconditionally(&data->ctx);
1597 	const struct adc_stm32_cfg *config = dev->config;
1598 	ADC_TypeDef *adc = config->base;
1636 	err = clock_control_off(clk, (clock_control_subsys_t)&config->pclken[0]);
1643 	err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
1644 	if ((err < 0) && (err != -ENOENT)) {
1646 		 * If returning -ENOENT, no pins where defined for sleep mode :
1667 		return -ENOTSUP;
1698 /* Concat prefix (1st element) and DIV value (2nd element) of st,adc-prescaler */
1763  * For some of the macros below, pseudo-code is provided to describe
1811  * Here is where both "first" and non-"first" instances have code