Lines Matching +full:adc +full:- +full:config
9 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/drivers/adc.h>
46 #include <zephyr/dt-bindings/adc/stm32_adc.h>
51 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
56 #include <zephyr/linker/linker-defs.h>
62 /* Here are some redefinitions of ADC versions for better readability */
80 * Other ADC versions:
81 * compat st_stm32f1_adc -> STM32F1, F37x (ADC1_V2_5)
82 * compat st_stm32f4_adc -> STM32F2, F4, F7, L1
119 /* reference voltage for the ADC */
194 static void adc_stm32_enable_dma_support(ADC_TypeDef *adc) in adc_stm32_enable_dma_support() argument
196 /* Allow ADC to create DMA request and set to one-shot mode as implemented in HAL drivers */ in adc_stm32_enable_dma_support()
198 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_UNLIMITED); in adc_stm32_enable_dma_support()
203 LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); in adc_stm32_enable_dma_support()
206 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED); in adc_stm32_enable_dma_support()
213 const struct adc_stm32_cfg *config = dev->config; in adc_stm32_dma_start() local
214 ADC_TypeDef *adc = config->base; in adc_stm32_dma_start() local
215 struct adc_stm32_data *data = dev->data; in adc_stm32_dma_start()
219 struct stream *dma = &data->dma; in adc_stm32_dma_start()
221 blk_cfg = &dma->dma_blk_cfg; in adc_stm32_dma_start()
224 blk_cfg->block_size = channel_count * sizeof(int16_t); in adc_stm32_dma_start()
227 blk_cfg->source_address = (uint32_t)LL_ADC_DMA_GetRegAddr(adc, LL_ADC_DMA_REG_REGULAR_DATA); in adc_stm32_dma_start()
228 blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in adc_stm32_dma_start()
229 blk_cfg->source_reload_en = 0; in adc_stm32_dma_start()
231 blk_cfg->dest_address = (uint32_t)buffer; in adc_stm32_dma_start()
232 blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in adc_stm32_dma_start()
233 blk_cfg->dest_reload_en = 0; in adc_stm32_dma_start()
238 blk_cfg->fifo_mode_control = 0; in adc_stm32_dma_start()
241 dma->dma_cfg.head_block = blk_cfg; in adc_stm32_dma_start()
242 dma->dma_cfg.user_data = data; in adc_stm32_dma_start()
244 ret = dma_config(data->dma.dma_dev, data->dma.channel, in adc_stm32_dma_start()
245 &dma->dma_cfg); in adc_stm32_dma_start()
251 adc_stm32_enable_dma_support(adc); in adc_stm32_dma_start()
253 data->dma_error = 0; in adc_stm32_dma_start()
254 ret = dma_start(data->dma.dma_dev, data->dma.channel); in adc_stm32_dma_start()
267 /* Returns true if given buffer is in a non-cacheable SRAM region.
272 * zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) | ... )>;
281 ((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end)); in buf_in_nocache()
301 if (sequence->options) { in check_buffer()
302 needed_buffer_size *= (1 + sequence->options->extra_samplings); in check_buffer()
305 if (sequence->buffer_size < needed_buffer_size) { in check_buffer()
307 sequence->buffer_size, needed_buffer_size); in check_buffer()
308 return -ENOMEM; in check_buffer()
312 /* Buffer is forced to be in non-cacheable SRAM region to avoid cache maintenance */ in check_buffer()
313 if (!buf_in_nocache((uintptr_t)sequence->buffer, needed_buffer_size)) { in check_buffer()
314 LOG_ERR("Supplied buffer is not in a non-cacheable region according to DTS."); in check_buffer()
315 return -EINVAL; in check_buffer()
323 * Enable ADC peripheral, and wait until ready if required by SOC.
325 static int adc_stm32_enable(ADC_TypeDef *adc) in adc_stm32_enable() argument
327 if (LL_ADC_IsEnabled(adc) == 1UL) { in adc_stm32_enable()
333 LL_ADC_ClearFlag_ADRDY(adc); in adc_stm32_enable()
334 LL_ADC_Enable(adc); in adc_stm32_enable()
337 * Enabling ADC modules in many series may fail if they are in adc_stm32_enable()
339 * to ensure ADC modules are properly enabled. in adc_stm32_enable()
343 while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) { in adc_stm32_enable()
346 if (LL_ADC_IsEnabled(adc) == 0UL) { in adc_stm32_enable()
347 LL_ADC_Enable(adc); in adc_stm32_enable()
353 return -ETIMEDOUT; in adc_stm32_enable()
358 * On STM32F1, F2, F37x, F4, F7 and L1, do not re-enable the ADC. in adc_stm32_enable()
362 LL_ADC_Enable(adc); in adc_stm32_enable()
370 const struct adc_stm32_cfg *config = dev->config; in adc_stm32_start_conversion() local
371 ADC_TypeDef *adc = config->base; in adc_stm32_start_conversion() local
377 LL_ADC_REG_StartConversion(adc); in adc_stm32_start_conversion()
379 LL_ADC_REG_StartConversionSWStart(adc); in adc_stm32_start_conversion()
384 * Disable ADC peripheral, and wait until it is disabled
386 static void adc_stm32_disable(ADC_TypeDef *adc) in adc_stm32_disable() argument
388 if (LL_ADC_IsEnabled(adc) != 1UL) { in adc_stm32_disable()
394 * the ADC is completely stopped. in adc_stm32_disable()
399 if (LL_ADC_REG_IsConversionOngoing(adc)) { in adc_stm32_disable()
400 LL_ADC_REG_StopConversion(adc); in adc_stm32_disable()
401 while (LL_ADC_REG_IsConversionOngoing(adc)) { in adc_stm32_disable()
415 if (LL_ADC_INJ_IsConversionOngoing(adc)) { in adc_stm32_disable()
416 LL_ADC_INJ_StopConversion(adc); in adc_stm32_disable()
417 while (LL_ADC_INJ_IsConversionOngoing(adc)) { in adc_stm32_disable()
422 LL_ADC_Disable(adc); in adc_stm32_disable()
424 /* Wait ADC is fully disabled so that we don't leave the driver into intermediate state in adc_stm32_disable()
427 while (LL_ADC_IsEnabled(adc) == 1UL) { in adc_stm32_disable()
435 /* Number of ADC clock cycles to wait before of after starting calibration */
449 * Other ADC modules have to wait for some cycles after calibration to in adc_stm32_calibration_delay()
452 const struct adc_stm32_cfg *config = dev->config; in adc_stm32_calibration_delay() local
457 (clock_control_subsys_t) &config->pclken[0], &adc_rate) < 0) { in adc_stm32_calibration_delay()
458 LOG_ERR("ADC clock rate get error."); in adc_stm32_calibration_delay()
462 LOG_ERR("ADC Clock rate null"); in adc_stm32_calibration_delay()
468 for (int i = wait_cycles; i >= 0; i--) { in adc_stm32_calibration_delay()
474 const struct adc_stm32_cfg *config = in adc_stm32_calibration_start() local
475 (const struct adc_stm32_cfg *)dev->config; in adc_stm32_calibration_start()
476 ADC_TypeDef *adc = config->base; in adc_stm32_calibration_start() local
485 LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED); in adc_stm32_calibration_start()
495 LL_ADC_StartCalibration(adc); in adc_stm32_calibration_start()
497 if (adc != ADC4) { in adc_stm32_calibration_start()
501 /* Some U5 implement an extended calibration to enhance ADC performance. in adc_stm32_calibration_start()
504 * The code below applies the procedure described in RM0456 in the ADC chapter: in adc_stm32_calibration_start()
508 adc_stm32_enable(adc); in adc_stm32_calibration_start()
509 MODIFY_REG(adc->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos); in adc_stm32_calibration_start()
511 MODIFY_REG(adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL); in adc_stm32_calibration_start()
513 SET_BIT(adc->CALFACT, ADC_CALFACT_LATCH_COEF); in adc_stm32_calibration_start()
514 adc_stm32_disable(adc); in adc_stm32_calibration_start()
517 LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET); in adc_stm32_calibration_start()
519 LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET, LL_ADC_SINGLE_ENDED); in adc_stm32_calibration_start()
522 * on the ADC control register, for enabling the peripheral for example in adc_stm32_calibration_start()
524 while (LL_ADC_IsCalibrationOnGoing(adc)) { in adc_stm32_calibration_start()
530 const struct adc_stm32_cfg *config = in adc_stm32_calibrate() local
531 (const struct adc_stm32_cfg *)dev->config; in adc_stm32_calibrate()
532 ADC_TypeDef *adc = config->base; in adc_stm32_calibrate() local
545 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE); in adc_stm32_calibrate()
547 if (adc == ADC4) { in adc_stm32_calibrate()
549 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE); in adc_stm32_calibrate()
555 adc_stm32_disable(adc); in adc_stm32_calibrate()
560 err = adc_stm32_enable(adc); in adc_stm32_calibrate()
579 if (adc == ADC1) { in adc_stm32_calibrate()
581 } else if (adc == ADC2) { in adc_stm32_calibrate()
593 adc, LL_ADC_CALIB_LINEARITY_WORD1 << count, in adc_stm32_calibrate()
639 * LL_ADC_SetOverSamplingScope() which in addition stops the ADC if needed.
641 static void adc_stm32_oversampling_scope(ADC_TypeDef *adc, uint32_t ovs_scope) in adc_stm32_oversampling_scope() argument
647 * Setting OVS bits is conditioned to ADC state: ADC must be disabled in adc_stm32_oversampling_scope()
649 * For the G0 series, ADC must be disabled to prevent CKMODE bitfield in adc_stm32_oversampling_scope()
652 if (LL_ADC_GetOverSamplingScope(adc) == ovs_scope) { in adc_stm32_oversampling_scope()
655 adc_stm32_disable(adc); in adc_stm32_oversampling_scope()
657 LL_ADC_SetOverSamplingScope(adc, ovs_scope); in adc_stm32_oversampling_scope()
663 * ADC if needed.
665 static void adc_stm32_oversampling_ratioshift(ADC_TypeDef *adc, uint32_t ratio, uint32_t shift) in adc_stm32_oversampling_ratioshift() argument
668 * setting OVS bits is conditioned to ADC state: ADC must be disabled in adc_stm32_oversampling_ratioshift()
671 if ((LL_ADC_GetOverSamplingRatio(adc) == ratio) in adc_stm32_oversampling_ratioshift()
672 && (LL_ADC_GetOverSamplingShift(adc) == shift)) { in adc_stm32_oversampling_ratioshift()
675 adc_stm32_disable(adc); in adc_stm32_oversampling_ratioshift()
677 LL_ADC_ConfigOverSamplingRatioShift(adc, ratio, shift); in adc_stm32_oversampling_ratioshift()
682 * ratio is directly the sequence->oversampling (a 2^n value)
687 const struct adc_stm32_cfg *config = dev->config; in adc_stm32_oversampling() local
688 ADC_TypeDef *adc = config->base; in adc_stm32_oversampling() local
691 adc_stm32_oversampling_scope(adc, LL_ADC_OVS_DISABLE); in adc_stm32_oversampling()
694 adc_stm32_oversampling_scope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED); in adc_stm32_oversampling()
697 return -EINVAL; in adc_stm32_oversampling()
703 if (config->oversampler_type == OVERSAMPLER_MINIMAL) { in adc_stm32_oversampling()
705 adc_stm32_oversampling_ratioshift(adc, table_oversampling_ratio[ratio], shift); in adc_stm32_oversampling()
710 if (config->oversampler_type == OVERSAMPLER_EXTENDED) { in adc_stm32_oversampling()
712 adc_stm32_oversampling_ratioshift(adc, 1 << ratio, shift); in adc_stm32_oversampling()
724 /* user_data directly holds the adc device */ in dma_callback()
727 const struct adc_stm32_cfg *config = data->dev->config; in dma_callback() local
728 ADC_TypeDef *adc = config->base; in dma_callback() local
733 if (channel == data->dma.channel) { in dma_callback()
735 if (LL_ADC_IsActiveFlag_OVR(adc)) { in dma_callback()
736 LL_ADC_ClearFlag_OVR(adc); in dma_callback()
737 LOG_ERR("ADC overrun error occurred. Reduce clock source frequency, " in dma_callback()
742 data->samples_count = data->channel_count; in dma_callback()
743 data->buffer += data->channel_count; in dma_callback()
749 dma_stop(data->dma.dma_dev, data->dma.channel); in dma_callback()
751 * the address is in a non-cacheable SRAM region. in dma_callback()
753 adc_context_on_sampling_done(&data->ctx, dev); in dma_callback()
762 data->dma_error = status; in dma_callback()
764 LL_ADC_REG_StopConversion(adc); in dma_callback()
766 dma_stop(data->dma.dma_dev, data->dma.channel); in dma_callback()
767 adc_context_complete(&data->ctx, status); in dma_callback()
776 const struct adc_stm32_cfg *config = dev->config; in get_reg_value() local
777 ADC_TypeDef *adc = config->base; in get_reg_value() local
779 uintptr_t addr = (uintptr_t)adc + reg; in get_reg_value()
787 const struct adc_stm32_cfg *config = dev->config; in set_reg_value() local
788 ADC_TypeDef *adc = config->base; in set_reg_value() local
790 uintptr_t addr = (uintptr_t)adc + reg; in set_reg_value()
798 const struct adc_stm32_cfg *config = dev->config; in set_resolution() local
799 ADC_TypeDef *adc = config->base; in set_resolution() local
806 for (i = 0; i < config->res_table_size; i++) { in set_resolution()
807 if (sequence->resolution == STM32_ADC_GET_REAL_VAL(config->res_table[i])) { in set_resolution()
808 res_reg_addr = STM32_ADC_GET_REG(config->res_table[i]); in set_resolution()
809 res_shift = STM32_ADC_GET_SHIFT(config->res_table[i]); in set_resolution()
810 res_mask = STM32_ADC_GET_MASK(config->res_table[i]); in set_resolution()
811 res_reg_val = STM32_ADC_GET_REG_VAL(config->res_table[i]); in set_resolution()
816 if (i == config->res_table_size) { in set_resolution()
818 return -EINVAL; in set_resolution()
837 * resets RES[1:0] bitfield. We need to disable and enable adc. in set_resolution()
839 adc_stm32_disable(adc); in set_resolution()
849 const struct adc_stm32_cfg *config = dev->config; in set_sequencer() local
850 struct adc_stm32_data *data = dev->data; in set_sequencer()
851 ADC_TypeDef *adc = config->base; in set_sequencer() local
858 * - channel_index: ranging from 0 -> ( data->channel_count - 1 ) in set_sequencer()
859 * - channel_id: ordinal position of channel in data->channels bitmask in set_sequencer()
861 for (uint32_t channels = data->channels; channels; in set_sequencer()
863 channel_id = find_lsb_set(channels) - 1; in set_sequencer()
870 if (config->sequencer_type == FULLY_CONFIGURABLE) { in set_sequencer()
876 LL_ADC_SetChannelPreselection(adc, channel); in set_sequencer()
878 LL_ADC_REG_SetSequencerRanks(adc, table_rank[channel_index], channel); in set_sequencer()
879 LL_ADC_REG_SetSequencerLength(adc, table_seq_len[channel_index]); in set_sequencer()
885 if (config->sequencer_type == NOT_FULLY_CONFIGURABLE) { in set_sequencer()
886 LL_ADC_REG_SetSequencerChannels(adc, channels_mask); in set_sequencer()
896 while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) { in set_sequencer()
898 LL_ADC_ClearFlag_CCRDY(adc); in set_sequencer()
905 LL_ADC_SetSequencersScanMode(adc, LL_ADC_SEQ_SCAN_ENABLE); in set_sequencer()
914 const struct adc_stm32_cfg *config = dev->config; in start_read() local
915 struct adc_stm32_data *data = dev->data; in start_read()
916 ADC_TypeDef *adc = config->base; in start_read() local
919 data->buffer = sequence->buffer; in start_read()
920 data->channels = sequence->channels; in start_read()
921 data->channel_count = POPCOUNT(data->channels); in start_read()
922 data->samples_count = 0; in start_read()
924 if (data->channel_count == 0) { in start_read()
926 return -EINVAL; in start_read()
930 if (data->channel_count > ARRAY_SIZE(table_seq_len)) { in start_read()
932 return -EINVAL; in start_read()
938 if (data->channel_count > 1) { in start_read()
940 return -EINVAL; in start_read()
956 err = check_buffer(sequence, data->channel_count); in start_read()
962 err = adc_stm32_oversampling(dev, sequence->oversampling); in start_read()
967 if (sequence->oversampling) { in start_read()
969 return -ENOTSUP; in start_read()
973 if (sequence->calibrate) { in start_read()
978 return -ENOTSUP; in start_read()
983 * Make sure the ADC is enabled as it might have been disabled earlier in start_read()
987 adc_stm32_enable(adc); in start_read()
990 LL_ADC_ClearFlag_OVR(adc); in start_read()
996 LL_ADC_REG_SetFlagEndOfConversion(adc, LL_ADC_REG_FLAG_EOC_UNITARY_CONV); in start_read()
997 LL_ADC_EnableIT_EOCS(adc); in start_read()
999 LL_ADC_EnableIT_EOS(adc); in start_read()
1001 LL_ADC_EnableIT_EOC(adc); in start_read()
1006 adc_context_start_read(&data->ctx, sequence); in start_read()
1008 int result = adc_context_wait_for_completion(&data->ctx); in start_read()
1012 result = (data->dma_error ? data->dma_error : result); in start_read()
1022 const struct device *dev = data->dev; in adc_context_start_sampling()
1023 const struct adc_stm32_cfg *config = dev->config; in adc_context_start_sampling() local
1024 ADC_TypeDef *adc = config->base; in adc_context_start_sampling() local
1027 ARG_UNUSED(adc); in adc_context_start_sampling()
1029 data->repeat_buffer = data->buffer; in adc_context_start_sampling()
1033 /* Make sure DMA bit of ADC register CR2 is set to 0 before starting a DMA transfer */ in adc_context_start_sampling()
1034 LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE); in adc_context_start_sampling()
1036 adc_stm32_dma_start(dev, data->buffer, data->channel_count); in adc_context_start_sampling()
1048 data->buffer = data->repeat_buffer; in adc_context_update_buffer_pointer()
1055 struct adc_stm32_data *data = dev->data;
1056 const struct adc_stm32_cfg *config = local
1057 (const struct adc_stm32_cfg *)dev->config;
1058 ADC_TypeDef *adc = config->base; local
1061 if (LL_ADC_IsActiveFlag_OVR(adc)) {
1062 LL_ADC_ClearFlag_OVR(adc);
1063 LOG_ERR("ADC overrun error occurred. Use DMA, reduce clock source frequency, "
1069 if (LL_ADC_IsActiveFlag_EOS(adc) == 1) {
1071 if (LL_ADC_IsActiveFlag_EOCS(adc) == 1) {
1073 if (LL_ADC_IsActiveFlag_EOC(adc) == 1) {
1075 *data->buffer++ = LL_ADC_REG_ReadConversionData32(adc);
1076 /* ISR is triggered after each conversion, and at the end-of-sequence. */
1077 if (++data->samples_count == data->channel_count) {
1078 data->samples_count = 0;
1079 adc_context_on_sampling_done(&data->ctx, dev);
1089 LOG_DBG("%s ISR triggered.", dev->name);
1097 const struct adc_stm32_cfg *config = data->dev->config; local
1098 ADC_TypeDef *adc = config->base; local
1103 data->acq_time_index[0] = -1;
1104 data->acq_time_index[1] = -1;
1108 LL_ADC_SetChannelPreselection(adc, 0);
1110 ARG_UNUSED(adc);
1117 struct adc_stm32_data *data = dev->data;
1120 adc_context_lock(&data->ctx, false, NULL);
1126 adc_context_release(&data->ctx, error);
1136 struct adc_stm32_data *data = dev->data;
1139 adc_context_lock(&data->ctx, true, async);
1145 adc_context_release(&data->ctx, error);
1153 const struct adc_stm32_cfg *config = local
1154 (const struct adc_stm32_cfg *)dev->config;
1161 return STM32_NB_SAMPLING_TIME - 1;
1166 config->sampling_time_table[i])) {
1172 return -EINVAL;
1178 const struct adc_stm32_cfg *config = local
1179 (const struct adc_stm32_cfg *)dev->config;
1180 ADC_TypeDef *adc = config->base; local
1181 struct adc_stm32_data *data = dev->data;
1196 switch (config->num_sampling_time_common_channels) {
1200 LL_ADC_SetChannelSamplingTime(adc,
1210 if ((data->acq_time_index[0] == -1) ||
1211 (acq_time_index == data->acq_time_index[0])) {
1213 data->acq_time_index[0] = acq_time_index;
1214 LL_ADC_SetSamplingTimeCommonChannels(adc,
1219 return -EINVAL;
1228 if ((data->acq_time_index[0] == -1) ||
1229 (acq_time_index == data->acq_time_index[0])) {
1231 data->acq_time_index[0] = acq_time_index;
1232 LL_ADC_SetChannelSamplingTime(adc,
1235 LL_ADC_SetSamplingTimeCommonChannels(adc,
1238 } else if ((data->acq_time_index[1] == -1) ||
1239 (acq_time_index == data->acq_time_index[1])) {
1241 data->acq_time_index[1] = acq_time_index;
1242 LL_ADC_SetChannelSamplingTime(adc,
1245 LL_ADC_SetSamplingTimeCommonChannels(adc,
1251 return -EINVAL;
1257 return -EINVAL;
1266 const struct adc_stm32_cfg *config = (const struct adc_stm32_cfg *)dev->config; local
1267 ADC_TypeDef *adc = config->base; local
1270 if (channel_cfg->differential) {
1272 return -EINVAL;
1275 if (channel_cfg->gain != ADC_GAIN_1) {
1277 return -EINVAL;
1280 if (channel_cfg->reference != ADC_REF_INTERNAL) {
1282 return -EINVAL;
1285 if (adc_stm32_sampling_time_setup(dev, channel_cfg->channel_id,
1286 channel_cfg->acquisition_time) != 0) {
1288 return -EINVAL;
1292 if (adc == ADC1) {
1293 if (channel_cfg->channel_id == 0) {
1294 LL_ADC_EnableChannel0_GPIO(adc);
1314 static bool adc_stm32_is_clk_sync(const struct adc_stm32_cfg *config) argument
1316 if (config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV1 ||
1317 config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV2 ||
1318 config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV4) {
1341 static int adc_stm32_get_clock_prescaler(const struct adc_stm32_cfg *config) argument
1343 switch (config->clk_prescaler) {
1372 return -EINVAL;
1376 static int adc_stm32h7_setup_boost(const struct adc_stm32_cfg *config, ADC_TypeDef *adc, argument
1385 clk_src = (clock_control_subsys_t)(adc_stm32_is_clk_sync(config) ? &config->pclken[0]
1386 : &config->pclken[1]);
1389 LOG_ERR("Failed to get ADC clock frequency");
1390 return -EIO;
1393 /* Adjust the pre-scaler value so that we can divide down the clock */
1394 presc = adc_stm32_get_clock_prescaler(config);
1413 LOG_WRN("ADC clock frequency too high %u", input_freq);
1414 return -ERANGE;
1417 LL_ADC_SetBoostMode(adc, boost);
1433 const struct adc_stm32_cfg *config = dev->config; local
1435 ADC_TypeDef *adc = config->base; local
1438 ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
1441 (clock_control_subsys_t) &config->pclken[0]) != 0) {
1442 return -EIO;
1445 if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) {
1446 /* Enable ADC clock source */
1448 (clock_control_subsys_t) &config->pclken[1],
1450 return -EIO;
1455 LL_ADC_SetClock(adc, config->clk_prescaler);
1457 if (adc_stm32_is_clk_sync(config)) {
1458 LL_ADC_SetClock(adc, config->clk_prescaler);
1460 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
1461 config->clk_prescaler);
1462 LL_ADC_SetClock(adc, LL_ADC_CLOCK_ASYNC);
1465 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
1466 config->clk_prescaler);
1470 ret = adc_stm32h7_setup_boost(config, adc, clk);
1479 struct adc_stm32_data *data = dev->data;
1480 const struct adc_stm32_cfg *config = dev->config; local
1482 ADC_TypeDef *adc = config->base; local
1485 ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
1487 LOG_DBG("Initializing %s", dev->name);
1491 return -ENODEV;
1494 data->dev = dev;
1498 * conversion time for all channels on one ADC instance has to
1505 data->acq_time_index[0] = -1;
1506 data->acq_time_index[1] = -1;
1510 /* Configure ADC inputs as specified in Device Tree, if any */
1511 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1512 if ((err < 0) && (err != -ENOENT)) {
1514 * If the ADC is used only with internal channels, then no pinctrl is
1515 * provided in Device Tree, and pinctrl_apply_state returns -ENOENT,
1518 LOG_ERR("ADC pinctrl setup failed (%d)", err);
1528 if ((data->dma.dma_dev != NULL) &&
1529 !device_is_ready(data->dma.dma_dev)) {
1530 LOG_ERR("%s device not ready", data->dma.dma_dev->name);
1531 return -ENODEV;
1548 LL_ADC_DisableDeepPowerDown(adc);
1552 * Many ADC modules need some time to be stabilized before performing
1558 LL_ADC_EnableInternalRegulator(adc);
1564 if (adc == ADC3) {
1567 while (LL_ADC_IsActiveFlag_LDORDY(adc) == 0) {
1573 while (LL_ADC_IsActiveFlag_LDORDY(adc) == 0) {
1580 if (config->irq_cfg_func) {
1581 config->irq_cfg_func();
1586 LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);
1589 adc_context_unlock_unconditionally(&data->ctx);
1597 const struct adc_stm32_cfg *config = dev->config; local
1598 ADC_TypeDef *adc = config->base; local
1602 /* Disable ADC */
1603 adc_stm32_disable(adc);
1608 /* Disable ADC internal voltage regulator */
1609 LL_ADC_DisableInternalRegulator(adc);
1610 while (LL_ADC_IsInternalRegulatorEnabled(adc) == 1U) {
1627 LL_ADC_EnableDeepPowerDown(adc);
1636 err = clock_control_off(clk, (clock_control_subsys_t)&config->pclken[0]);
1638 LOG_ERR("Could not disable ADC clock");
1643 err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
1644 if ((err < 0) && (err != -ENOENT)) {
1646 * If returning -ENOENT, no pins where defined for sleep mode :
1648 * "ADC pinctrl sleep state not available"
1667 return -ENOTSUP;
1674 static DEVICE_API(adc, api_stm32_driver_api) = {
1698 /* Concat prefix (1st element) and DIV value (2nd element) of st,adc-prescaler */
1705 /* Macro to check if the ADC instance clock setup is correct */
1745 * For series that share interrupt lines for multiple ADC instances
1747 * STM32G473 has 5 ADC instances, ADC1 and ADC2 share IRQn 18 while
1752 * To achieve the above, a "first" ADC instance must be chosen for all
1753 * ADC instances sharing the same IRQn. This "first" ADC instance
1755 * enabling it while any other ADC sharing the same IRQn skips this
1759 * for IRQn 18, 47, 61 and 62, with possible "first" ADC instances
1763 * For some of the macros below, pseudo-code is provided to describe
1801 * given index). Example, for an ADC instance with IRQn 18, returns
1808 * ADC instances that share the same IRQn as that of the given device
1811 * Here is where both "first" and non-"first" instances have code
1850 (/* Required for other adc instances without dma */))