16 #include <zephyr/drivers/adc.h>
46 #include <zephyr/dt-bindings/adc/stm32_adc.h>
62 /* Here are some redefinitions of ADC versions for better readability */
80  * Other ADC versions:
119 /* reference voltage for the ADC */
194 static void adc_stm32_enable_dma_support(ADC_TypeDef *adc)  in adc_stm32_enable_dma_support()  argument
196 	/* Allow ADC to create DMA request and set to one-shot mode as implemented in HAL drivers */  in adc_stm32_enable_dma_support()
198 	LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_UNLIMITED);  in adc_stm32_enable_dma_support()
203 	LL_ADC_REG_SetDataTransferMode(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED);  in adc_stm32_enable_dma_support()
206 	LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_LIMITED);  in adc_stm32_enable_dma_support()
214 	ADC_TypeDef *adc = config->base;  in adc_stm32_dma_start()  local
227 	blk_cfg->source_address = (uint32_t)LL_ADC_DMA_GetRegAddr(adc, LL_ADC_DMA_REG_REGULAR_DATA);  in adc_stm32_dma_start()
251 	adc_stm32_enable_dma_support(adc);  in adc_stm32_dma_start()
323  * Enable ADC peripheral, and wait until ready if required by SOC.
325 static int adc_stm32_enable(ADC_TypeDef *adc)  in adc_stm32_enable()  argument
327 	if (LL_ADC_IsEnabled(adc) == 1UL) {  in adc_stm32_enable()
333 	LL_ADC_ClearFlag_ADRDY(adc);  in adc_stm32_enable()
334 	LL_ADC_Enable(adc);  in adc_stm32_enable()
337 	 * Enabling ADC modules in many series may fail if they are  in adc_stm32_enable()
339 	 * to ensure ADC modules are properly enabled.  in adc_stm32_enable()
343 	while (LL_ADC_IsActiveFlag_ADRDY(adc) == 0) {  in adc_stm32_enable()
346 		if (LL_ADC_IsEnabled(adc) == 0UL) {  in adc_stm32_enable()
347 			LL_ADC_Enable(adc);  in adc_stm32_enable()
358 	 * On STM32F1, F2, F37x, F4, F7 and L1, do not re-enable the ADC.  in adc_stm32_enable()
362 	LL_ADC_Enable(adc);  in adc_stm32_enable()
371 	ADC_TypeDef *adc = config->base;  in adc_stm32_start_conversion()  local
377 	LL_ADC_REG_StartConversion(adc);  in adc_stm32_start_conversion()
379 	LL_ADC_REG_StartConversionSWStart(adc);  in adc_stm32_start_conversion()
384  * Disable ADC peripheral, and wait until it is disabled
386 static void adc_stm32_disable(ADC_TypeDef *adc)  in adc_stm32_disable()  argument
388 	if (LL_ADC_IsEnabled(adc) != 1UL) {  in adc_stm32_disable()
394 	 * the ADC is completely stopped.  in adc_stm32_disable()
399 	if (LL_ADC_REG_IsConversionOngoing(adc)) {  in adc_stm32_disable()
400 		LL_ADC_REG_StopConversion(adc);  in adc_stm32_disable()
401 		while (LL_ADC_REG_IsConversionOngoing(adc)) {  in adc_stm32_disable()
415 	if (LL_ADC_INJ_IsConversionOngoing(adc)) {  in adc_stm32_disable()
416 		LL_ADC_INJ_StopConversion(adc);  in adc_stm32_disable()
417 		while (LL_ADC_INJ_IsConversionOngoing(adc)) {  in adc_stm32_disable()
422 	LL_ADC_Disable(adc);  in adc_stm32_disable()
424 	/* Wait ADC is fully disabled so that we don't leave the driver into intermediate state  in adc_stm32_disable()
427 	while (LL_ADC_IsEnabled(adc) == 1UL) {  in adc_stm32_disable()
435 /* Number of ADC clock cycles to wait before of after starting calibration */
449 	 * Other ADC modules have to wait for some cycles after calibration to  in adc_stm32_calibration_delay()
458 		LOG_ERR("ADC clock rate get error.");  in adc_stm32_calibration_delay()
462 		LOG_ERR("ADC Clock rate null");  in adc_stm32_calibration_delay()
476 	ADC_TypeDef *adc = config->base;  in adc_stm32_calibration_start()  local
485 	LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);  in adc_stm32_calibration_start()
495 	LL_ADC_StartCalibration(adc);  in adc_stm32_calibration_start()
497 	if (adc != ADC4) {  in adc_stm32_calibration_start()
501 		/* Some U5 implement an extended calibration to enhance ADC performance.  in adc_stm32_calibration_start()
504 		 * The code below applies the procedure described in RM0456 in the ADC chapter:  in adc_stm32_calibration_start()
508 			adc_stm32_enable(adc);  in adc_stm32_calibration_start()
509 			MODIFY_REG(adc->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos);  in adc_stm32_calibration_start()
511 			MODIFY_REG(adc->CALFACT2, 0xFFFFFF00UL, 0x03021100UL);  in adc_stm32_calibration_start()
513 			SET_BIT(adc->CALFACT, ADC_CALFACT_LATCH_COEF);  in adc_stm32_calibration_start()
514 			adc_stm32_disable(adc);  in adc_stm32_calibration_start()
517 	LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET);  in adc_stm32_calibration_start()
519 	LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET, LL_ADC_SINGLE_ENDED);  in adc_stm32_calibration_start()
522 	 * on the ADC control register, for enabling the peripheral for example  in adc_stm32_calibration_start()
524 	while (LL_ADC_IsCalibrationOnGoing(adc)) {  in adc_stm32_calibration_start()
532 	ADC_TypeDef *adc = config->base;  in adc_stm32_calibrate()  local
545 	LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE);  in adc_stm32_calibrate()
547 	if (adc == ADC4) {  in adc_stm32_calibrate()
549 		LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE);  in adc_stm32_calibrate()
555 	adc_stm32_disable(adc);  in adc_stm32_calibrate()
560 	err = adc_stm32_enable(adc);  in adc_stm32_calibrate()
579 	if (adc == ADC1) {  in adc_stm32_calibrate()
581 	} else if (adc == ADC2) {  in adc_stm32_calibrate()
593 			adc, LL_ADC_CALIB_LINEARITY_WORD1 << count,  in adc_stm32_calibrate()
639  * LL_ADC_SetOverSamplingScope() which in addition stops the ADC if needed.
641 static void adc_stm32_oversampling_scope(ADC_TypeDef *adc, uint32_t ovs_scope)  in adc_stm32_oversampling_scope()  argument
647 	 * Setting OVS bits is conditioned to ADC state: ADC must be disabled  in adc_stm32_oversampling_scope()
649 	 * For the G0 series, ADC must be disabled to prevent CKMODE bitfield  in adc_stm32_oversampling_scope()
652 	if (LL_ADC_GetOverSamplingScope(adc) == ovs_scope) {  in adc_stm32_oversampling_scope()
655 	adc_stm32_disable(adc);  in adc_stm32_oversampling_scope()
657 	LL_ADC_SetOverSamplingScope(adc, ovs_scope);  in adc_stm32_oversampling_scope()
663  * ADC if needed.
665 static void adc_stm32_oversampling_ratioshift(ADC_TypeDef *adc, uint32_t ratio, uint32_t shift)  in adc_stm32_oversampling_ratioshift()  argument
668 	 * setting OVS bits is conditioned to ADC state: ADC must be disabled  in adc_stm32_oversampling_ratioshift()
671 	if ((LL_ADC_GetOverSamplingRatio(adc) == ratio)  in adc_stm32_oversampling_ratioshift()
672 	    && (LL_ADC_GetOverSamplingShift(adc) == shift)) {  in adc_stm32_oversampling_ratioshift()
675 	adc_stm32_disable(adc);  in adc_stm32_oversampling_ratioshift()
677 	LL_ADC_ConfigOverSamplingRatioShift(adc, ratio, shift);  in adc_stm32_oversampling_ratioshift()
688 	ADC_TypeDef *adc = config->base;  in adc_stm32_oversampling()  local
691 		adc_stm32_oversampling_scope(adc, LL_ADC_OVS_DISABLE);  in adc_stm32_oversampling()
694 		adc_stm32_oversampling_scope(adc, LL_ADC_OVS_GRP_REGULAR_CONTINUED);  in adc_stm32_oversampling()
705 		adc_stm32_oversampling_ratioshift(adc, table_oversampling_ratio[ratio], shift);  in adc_stm32_oversampling()
712 		adc_stm32_oversampling_ratioshift(adc, 1 << ratio, shift);  in adc_stm32_oversampling()
724 	/* user_data directly holds the adc device */  in dma_callback()
728 	ADC_TypeDef *adc = config->base;  in dma_callback()  local
735 		if (LL_ADC_IsActiveFlag_OVR(adc)) {  in dma_callback()
736 			LL_ADC_ClearFlag_OVR(adc);  in dma_callback()
737 			LOG_ERR("ADC overrun error occurred. Reduce clock source frequency, "  in dma_callback()
764 			LL_ADC_REG_StopConversion(adc);  in dma_callback()
777 	ADC_TypeDef *adc = config->base;  in get_reg_value()  local
779 	uintptr_t addr = (uintptr_t)adc + reg;  in get_reg_value()
788 	ADC_TypeDef *adc = config->base;  in set_reg_value()  local
790 	uintptr_t addr = (uintptr_t)adc + reg;  in set_reg_value()
799 	ADC_TypeDef *adc = config->base;  in set_resolution()  local
837 			 * resets RES[1:0] bitfield. We need to disable and enable adc.  in set_resolution()
839 			adc_stm32_disable(adc);  in set_resolution()
851 	ADC_TypeDef *adc = config->base;  in set_sequencer()  local
876 			LL_ADC_SetChannelPreselection(adc, channel);  in set_sequencer()
878 			LL_ADC_REG_SetSequencerRanks(adc, table_rank[channel_index], channel);  in set_sequencer()
879 			LL_ADC_REG_SetSequencerLength(adc, table_seq_len[channel_index]);  in set_sequencer()
886 		LL_ADC_REG_SetSequencerChannels(adc, channels_mask);  in set_sequencer()
896 		while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) {  in set_sequencer()
898 		LL_ADC_ClearFlag_CCRDY(adc);  in set_sequencer()
905 	LL_ADC_SetSequencersScanMode(adc, LL_ADC_SEQ_SCAN_ENABLE);  in set_sequencer()
916 	ADC_TypeDef *adc = config->base;  in start_read()  local
983 	 * Make sure the ADC is enabled as it might have been disabled earlier  in start_read()
987 	adc_stm32_enable(adc);  in start_read()
990 	LL_ADC_ClearFlag_OVR(adc);  in start_read()
996 	LL_ADC_REG_SetFlagEndOfConversion(adc, LL_ADC_REG_FLAG_EOC_UNITARY_CONV);  in start_read()
997 	LL_ADC_EnableIT_EOCS(adc);  in start_read()
999 	LL_ADC_EnableIT_EOS(adc);  in start_read()
1001 	LL_ADC_EnableIT_EOC(adc);  in start_read()
1024 	ADC_TypeDef *adc = config->base;  in adc_context_start_sampling()  local
1027 	ARG_UNUSED(adc);  in adc_context_start_sampling()
1033 	/* Make sure DMA bit of ADC register CR2 is set to 0 before starting a DMA transfer */  in adc_context_start_sampling()
1034 	LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_NONE);  in adc_context_start_sampling()
1058 	ADC_TypeDef *adc = config->base;  local
1061 	if (LL_ADC_IsActiveFlag_OVR(adc)) {
1062 		LL_ADC_ClearFlag_OVR(adc);
1063 		LOG_ERR("ADC overrun error occurred. Use DMA, reduce clock source frequency, "
1069 	if (LL_ADC_IsActiveFlag_EOS(adc) == 1) {
1071 	if (LL_ADC_IsActiveFlag_EOCS(adc) == 1) {
1073 	if (LL_ADC_IsActiveFlag_EOC(adc) == 1) {
1075 		*data->buffer++ = LL_ADC_REG_ReadConversionData32(adc);
1098 	ADC_TypeDef *adc = config->base;  local
1108 	LL_ADC_SetChannelPreselection(adc, 0);
1110 	ARG_UNUSED(adc);
1180 	ADC_TypeDef *adc = config->base;  local
1200 		LL_ADC_SetChannelSamplingTime(adc,
1214 			LL_ADC_SetSamplingTimeCommonChannels(adc,
1232 			LL_ADC_SetChannelSamplingTime(adc,
1235 			LL_ADC_SetSamplingTimeCommonChannels(adc,
1242 			LL_ADC_SetChannelSamplingTime(adc,
1245 			LL_ADC_SetSamplingTimeCommonChannels(adc,
1267 	ADC_TypeDef *adc = config->base;  local
1292 	if (adc == ADC1) {
1294 			LL_ADC_EnableChannel0_GPIO(adc);
1376 static int adc_stm32h7_setup_boost(const struct adc_stm32_cfg *config, ADC_TypeDef *adc,  argument
1389 		LOG_ERR("Failed to get ADC clock frequency");
1413 		LOG_WRN("ADC clock frequency too high %u", input_freq);
1417 	LL_ADC_SetBoostMode(adc, boost);
1435 	ADC_TypeDef *adc = config->base;  local
1438 	ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
1446 		/* Enable ADC clock source */
1455 	LL_ADC_SetClock(adc, config->clk_prescaler);
1458 		LL_ADC_SetClock(adc, config->clk_prescaler);
1460 		LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
1462 		LL_ADC_SetClock(adc, LL_ADC_CLOCK_ASYNC);
1465 	LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
1470 	ret = adc_stm32h7_setup_boost(config, adc, clk);
1482 	ADC_TypeDef *adc = config->base;  local
1485 	ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
1498 	 * conversion time for all channels on one ADC instance has to
1510 	/* Configure ADC inputs as specified in Device Tree, if any */
1514 		 * If the ADC is used only with internal channels, then no pinctrl is
1518 		LOG_ERR("ADC pinctrl setup failed (%d)", err);
1548 	LL_ADC_DisableDeepPowerDown(adc);
1552 	 * Many ADC modules need some time to be stabilized before performing
1558 	LL_ADC_EnableInternalRegulator(adc);
1564 	if (adc == ADC3) {
1567 		while (LL_ADC_IsActiveFlag_LDORDY(adc) == 0) {
1573 	while (LL_ADC_IsActiveFlag_LDORDY(adc) == 0) {
1586 	LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);
1598 	ADC_TypeDef *adc = config->base;  local
1602 	/* Disable ADC */
1603 	adc_stm32_disable(adc);
1608 	/* Disable ADC internal voltage regulator */
1609 	LL_ADC_DisableInternalRegulator(adc);
1610 	while (LL_ADC_IsInternalRegulatorEnabled(adc) == 1U) {
1627 	LL_ADC_EnableDeepPowerDown(adc);
1638 		LOG_ERR("Could not disable ADC clock");
1648 		 * "ADC pinctrl sleep state not available"
1674 static DEVICE_API(adc, api_stm32_driver_api) = {
1698 /* Concat prefix (1st element) and DIV value (2nd element) of st,adc-prescaler */
1705 /* Macro to check if the ADC instance clock setup is correct */
1745  * For series that share interrupt lines for multiple ADC instances
1747  * STM32G473 has 5 ADC instances, ADC1 and ADC2 share IRQn 18 while
1752  * To achieve the above, a "first" ADC instance must be chosen for all
1753  * ADC instances sharing the same IRQn. This "first" ADC instance
1755  * enabling it while any other ADC sharing the same IRQn skips this
1759  * for IRQn 18, 47, 61 and 62, with possible "first" ADC instances
1801  * given index). Example, for an ADC instance with IRQn 18, returns
1808  * ADC instances that share the same IRQn as that of the given device
1850 			(/* Required for other adc instances without dma */))