Lines Matching +full:0 +full:x00 +full:- +full:positive
4 * SPDX-License-Identifier: Apache-2.0
27 #define MAX1125X_CMD_READ 0xC1
28 #define MAX1125X_CMD_WRITE 0xC0
29 #define MAX1125X_CMD_CONV 0x80
30 #define MAX1125X_CMD_CALIBRATION 0x20
31 #define MAX1125X_CMD_SEQUENCER 0x30
34 MAX1125X_MODE_POWERDOWN = 0x01,
35 MAX1125X_MODE_CALIBRATION = 0x02,
36 MAX1125X_MODE_SEQUENCER = 0x03,
40 MAX1125X_CONFIG_RATE_1_9 = 0x00,
41 MAX1125X_CONFIG_RATE_3_9 = 0x01,
42 MAX1125X_CONFIG_RATE_7_8 = 0x02,
43 MAX1125X_CONFIG_RATE_15_6 = 0x03,
44 MAX1125X_CONFIG_RATE_31_2 = 0x04,
45 MAX1125X_CONFIG_RATE_62_5 = 0x05,
46 MAX1125X_CONFIG_RATE_125 = 0x06,
47 MAX1125X_CONFIG_RATE_250 = 0x07,
48 MAX1125X_CONFIG_RATE_500 = 0x08,
49 MAX1125X_CONFIG_RATE_1000 = 0x09,
50 MAX1125X_CONFIG_RATE_2000 = 0x0A,
51 MAX1125X_CONFIG_RATE_4000 = 0x0B,
52 MAX1125X_CONFIG_RATE_8000 = 0x0C,
53 MAX1125X_CONFIG_RATE_16000 = 0x0D,
54 MAX1125X_CONFIG_RATE_32000 = 0x0E,
55 MAX1125X_CONFIG_RATE_64000 = 0x0F,
59 MAX1125X_REG_STAT = 0x00,
60 MAX1125X_REG_CTRL1 = 0x02,
61 MAX1125X_REG_CTRL2 = 0x04,
62 MAX1125X_REG_CTRL3 = 0x06,
63 MAX1125X_REG_GPIO_CTRL = 0x08,
64 MAX1125X_REG_DELAY = 0x0A,
65 MAX1125X_REG_CHMAP1 = 0x0C,
66 MAX1125X_REG_CHMAP0 = 0x0E,
67 MAX1125X_REG_SEQ = 0x10,
68 MAX1125X_REG_GPO_DIR = 0x12,
69 MAX1125X_REG_SOC = 0x14,
70 MAX1125X_REG_SGC = 0x16,
71 MAX1125X_REG_SCOC = 0x18,
72 MAX1125X_REG_SCGC = 0x1A,
73 MAX1125X_REG_DATA0 = 0x1C,
74 MAX1125X_REG_DATA1 = 0x1E,
75 MAX1125X_REG_DATA2 = 0x20,
76 MAX1125X_REG_DATA3 = 0x22,
77 MAX1125X_REG_DATA4 = 0x24,
78 MAX1125X_REG_DATA5 = 0x26,
99 MAX1125X_CTRL1_CAL_SELF = 0,
105 MAX1125X_CTRL1_PD_NOP = 0,
112 MAX1125X_CTRL1_CONTSC = 0,
119 MAX1125X_CTRL2_PGA_GAIN_1 = 0,
138 MAX1125X_CTRL3_NOSCO = 0,
148 MAX1125X_GPIO_CTRL_DIO0 = 0,
157 MAX1125X_SEQ_RDYBEN = 0,
168 MAX1125X_GPO_DIR_GPO0 = 0,
173 MAX1125X_CMD_RATE0 = 0,
180 MAX1125X_CHANNEL_0 = 0x0,
181 MAX1125X_CHANNEL_1 = 0x1,
182 MAX1125X_CHANNEL_2 = 0x2,
183 MAX1125X_CHANNEL_3 = 0x3,
184 MAX1125X_CHANNEL_4 = 0x4,
185 MAX1125X_CHANNEL_5 = 0x5,
241 k_sem_give(&data->data_ready_signal); in max1125x_data_ready_handler()
248 const struct max1125x_config *config = dev->config; in max1125x_read_reg()
267 buffer_tx[0] = MAX1125X_CMD_READ | reg_addr; in max1125x_read_reg()
269 buffer_tx[1] = 0x00; in max1125x_read_reg()
271 ret = spi_transceive_dt(&config->bus, &tx, &rx); in max1125x_read_reg()
272 if (ret != 0) { in max1125x_read_reg()
273 LOG_ERR("MAX1125X: error writing register 0x%X (%d)", reg_addr, ret); in max1125x_read_reg()
277 LOG_DBG("read from register 0x%02X value 0x%02X", reg_addr, *buffer); in max1125x_read_reg()
279 return 0; in max1125x_read_reg()
286 const struct max1125x_config *config = dev->config; in max1125x_write_reg()
293 ret = spi_write_dt(&config->bus, &tx); in max1125x_write_reg()
294 if (ret != 0) { in max1125x_write_reg()
295 LOG_ERR("MAX1125X: error writing register 0x%X (%d)", reg_addr, ret); in max1125x_write_reg()
299 return 0; in max1125x_write_reg()
305 const struct max1125x_config *config = dev->config; in max1125x_send_command()
310 ret = spi_write_dt(&config->bus, &tx); in max1125x_send_command()
311 if (ret != 0) { in max1125x_send_command()
312 LOG_ERR("MAX1125X: error writing register 0x%X (%d)", rate, ret); in max1125x_send_command()
316 return 0; in max1125x_send_command()
321 const struct max1125x_data *data = dev->data; in max1125x_start_conversion()
323 return max1125x_send_command(dev, MAX1125X_CMD_SEQUENCER, data->rate); in max1125x_start_conversion()
328 struct max1125x_data *data = dev->data; in max1125x_acq_time_to_dr()
329 const struct max1125x_config *config = dev->config; in max1125x_acq_time_to_dr()
330 const uint32_t *odr_delay = config->odr_delay; in max1125x_acq_time_to_dr()
331 uint32_t odr_delay_us = 0; in max1125x_acq_time_to_dr()
333 int odr = -EINVAL; in max1125x_acq_time_to_dr()
337 return -EINVAL; in max1125x_acq_time_to_dr()
342 return -EINVAL; in max1125x_acq_time_to_dr()
348 data->rate = odr; in max1125x_acq_time_to_dr()
355 struct max1125x_data *data = dev->data; in max1125x_wait_data_ready()
357 return k_sem_take(&data->data_ready_signal, ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT); in max1125x_wait_data_ready()
362 const struct max1125x_config *config = dev->config; in max1125x_read_sample()
363 struct max1125x_data *data = dev->data; in max1125x_read_sample()
365 uint8_t buffer_tx[(config->resolution / 8) + 1]; in max1125x_read_sample()
367 uint8_t current_channel = find_msb_set(data->ctx.sequence.channels) - 1; in max1125x_read_sample()
387 buffer_tx[0] = MAX1125X_CMD_READ | MAX1125X_REG_DATA(current_channel); in max1125x_read_sample()
389 rc = spi_transceive_dt(&config->bus, &tx, &rx); in max1125x_read_sample()
390 if (rc != 0) { in max1125x_read_sample()
396 * In offset binary format the most negative value is 0x000000, in max1125x_read_sample()
397 * the midscale value is 0x800000 and the most positive value is in max1125x_read_sample()
398 * 0xFFFFFF. In bipolar mode if the FORMAT bit = ‘1’ then the in max1125x_read_sample()
399 * data format is offset binary. If the FORMAT bit = ‘0’, then in max1125x_read_sample()
401 * negative full-scale value is 0x800000, the midscale is 0x000000 in max1125x_read_sample()
402 * and the positive full scale is 0x7FFFFF. Any input exceeding in max1125x_read_sample()
406 is_positive = buffer_rx[(config->resolution / 8)] >> 7; in max1125x_read_sample()
408 *data->buffer++ = sys_get_be24(buffer_rx) - (1 << (config->resolution - 1)); in max1125x_read_sample()
410 *data->buffer++ = sys_get_be24(buffer_rx + 1); in max1125x_read_sample()
413 adc_context_on_sampling_done(&data->ctx, dev); in max1125x_read_sample()
420 uint8_t last_order = 0; in max1125x_configure_chmap()
421 uint8_t chmap1_register[3] = {0}; in max1125x_configure_chmap()
422 uint8_t chmap0_register[3] = {0}; in max1125x_configure_chmap()
426 return -EINVAL; in max1125x_configure_chmap()
430 for (int index = 0; index < 3; index++) { in max1125x_configure_chmap()
439 for (int index = 0; index < 3; index++) { in max1125x_configure_chmap()
457 chmap0_register[0] = MAX1125X_CONFIG_CHMAP(last_order); in max1125x_configure_chmap()
466 chmap1_register[0] = MAX1125X_CONFIG_CHMAP(last_order); in max1125x_configure_chmap()
477 /* CHMAP 0 register configuration */ in max1125x_configure_chmap()
482 return 0; in max1125x_configure_chmap()
487 uint8_t seq_register = 0; in max1125x_self_calibration()
492 max1125x_send_command(dev, MAX1125X_CMD_CALIBRATION, 0x00); in max1125x_self_calibration()
495 return 0; in max1125x_self_calibration()
501 const struct max1125x_config *max_config = dev->config; in max1125x_channel_setup()
502 uint8_t seq_register = 0; in max1125x_channel_setup()
503 uint8_t ctrl2_register = 0; in max1125x_channel_setup()
504 uint8_t gpio_reg = 0; in max1125x_channel_setup()
505 uint8_t gpo_reg = 0; in max1125x_channel_setup()
514 if (max_config->multiplexer) { in max1125x_channel_setup()
515 if (!channel_cfg->differential) { in max1125x_channel_setup()
518 channel_cfg->differential); in max1125x_channel_setup()
519 return -ENOTSUP; in max1125x_channel_setup()
523 max1125x_acq_time_to_dr(dev, channel_cfg->acquisition_time); in max1125x_channel_setup()
526 if (max_config->pga) { in max1125x_channel_setup()
529 switch (channel_cfg->gain) { in max1125x_channel_setup()
555 LOG_ERR("MAX1125X: unsupported channel gain '%d'", channel_cfg->gain); in max1125x_channel_setup()
556 return -ENOTSUP; in max1125x_channel_setup()
560 if (channel_cfg->reference == ADC_REF_INTERNAL) { in max1125x_channel_setup()
563 } else if (channel_cfg->reference == ADC_REF_EXTERNAL1) { in max1125x_channel_setup()
567 channel_cfg->reference); in max1125x_channel_setup()
568 return -ENOTSUP; in max1125x_channel_setup()
573 gpio_reg |= max_config->gpio.gpio0_enable << MAX1125X_GPIO_CTRL_GPIO0_EN; in max1125x_channel_setup()
574 gpio_reg |= max_config->gpio.gpio1_enable << MAX1125X_GPIO_CTRL_GPIO1_EN; in max1125x_channel_setup()
575 gpio_reg |= max_config->gpio.gpio0_direction << MAX1125X_GPIO_CTRL_DIRO; in max1125x_channel_setup()
576 gpio_reg |= max_config->gpio.gpio1_direction << MAX1125X_GPIO_CTRL_DIR1; in max1125x_channel_setup()
580 gpo_reg |= max_config->gpo.gpo0_enable << MAX1125X_GPO_DIR_GPO0; in max1125x_channel_setup()
581 gpo_reg |= max_config->gpo.gpo1_enable << MAX1125X_GPO_DIR_GPO1; in max1125x_channel_setup()
585 max1125x_configure_chmap(dev, channel_cfg->channel_id); in max1125x_channel_setup()
587 return 0; in max1125x_channel_setup()
592 size_t needed = sizeof(uint8_t) * (sequence->resolution / 8); in max1125x_validate_buffer_size()
594 if (sequence->options) { in max1125x_validate_buffer_size()
595 needed *= (1 + sequence->options->extra_samplings); in max1125x_validate_buffer_size()
598 if (sequence->buffer_size < needed) { in max1125x_validate_buffer_size()
599 return -ENOMEM; in max1125x_validate_buffer_size()
602 return 0; in max1125x_validate_buffer_size()
609 if (sequence->oversampling) { in max1125x_validate_sequence()
611 return -ENOTSUP; in max1125x_validate_sequence()
617 return -ENOTSUP; in max1125x_validate_sequence()
620 return 0; in max1125x_validate_sequence()
628 data->buffer = data->repeat_buffer; in adc_context_update_buffer_pointer()
636 data->repeat_buffer = data->buffer; in adc_context_start_sampling()
638 max1125x_start_conversion(data->dev); in adc_context_start_sampling()
640 k_sem_give(&data->acq_sem); in adc_context_start_sampling()
646 struct max1125x_data *data = dev->data; in max1125x_adc_start_read()
649 if (rc != 0) { in max1125x_adc_start_read()
653 data->buffer = sequence->buffer; in max1125x_adc_start_read()
655 adc_context_start_read(&data->ctx, sequence); in max1125x_adc_start_read()
657 return adc_context_wait_for_completion(&data->ctx); in max1125x_adc_start_read()
664 struct max1125x_data *data = dev->data; in max1125x_adc_read_async()
666 adc_context_lock(&data->ctx, async ? true : false, async); in max1125x_adc_read_async()
668 adc_context_release(&data->ctx, rc); in max1125x_adc_read_async()
675 struct max1125x_data *data = dev->data; in max1125x_adc_perform_read()
679 if (rc != 0) { in max1125x_adc_perform_read()
681 adc_context_complete(&data->ctx, rc); in max1125x_adc_perform_read()
699 struct max1125x_data *data = dev->data; in max1125x_acquisition_thread()
703 k_sem_take(&data->acq_sem, K_FOREVER); in max1125x_acquisition_thread()
706 if (rc != 0) { in max1125x_acquisition_thread()
708 adc_context_complete(&data->ctx, rc); in max1125x_acquisition_thread()
719 const struct max1125x_config *config = dev->config; in max1125x_init()
720 struct max1125x_data *data = dev->data; in max1125x_init()
722 data->dev = dev; in max1125x_init()
724 k_sem_init(&data->acq_sem, 0, 1); in max1125x_init()
725 k_sem_init(&data->data_ready_signal, 0, 1); in max1125x_init()
727 if (!spi_is_ready_dt(&config->bus)) { in max1125x_init()
728 LOG_ERR("spi bus %s not ready", config->bus.bus->name); in max1125x_init()
729 return -ENODEV; in max1125x_init()
732 if (config->self_calibration) { in max1125x_init()
737 err = gpio_pin_configure_dt(&config->drdy_gpio, GPIO_INPUT); in max1125x_init()
738 if (err != 0) { in max1125x_init()
743 err = gpio_pin_interrupt_configure_dt(&config->drdy_gpio, GPIO_INT_EDGE_TO_ACTIVE); in max1125x_init()
744 if (err != 0) { in max1125x_init()
746 return -EIO; in max1125x_init()
749 gpio_init_callback(&data->callback_data_ready, max1125x_data_ready_handler, in max1125x_init()
750 BIT(config->drdy_gpio.pin)); in max1125x_init()
751 err = gpio_add_callback(config->drdy_gpio.port, &data->callback_data_ready); in max1125x_init()
752 if (err != 0) { in max1125x_init()
754 return -EIO; in max1125x_init()
758 &data->thread, data->stack, K_KERNEL_STACK_SIZEOF(data->stack), in max1125x_init()
760 CONFIG_ADC_MAX1125X_ACQUISITION_THREAD_PRIORITY, 0, K_NO_WAIT); in max1125x_init()
763 adc_context_unlock_unconditionally(&data->ctx); in max1125x_init()
765 return 0; in max1125x_init()
788 .drdy_gpio = GPIO_DT_SPEC_GET_OR(DT_INST_MAX1125X(n, t), drdy_gpios, {0}), \
789 .self_calibration = DT_PROP_OR(DT_INST_MAX1125X(n, t), self_calibration, 0), \
791 .gpio.gpio1_enable = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpio1_enable, 0), \
792 .gpio.gpio0_direction = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpio0_direction, 0), \
793 .gpio.gpio1_direction = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpio1_direction, 0), \
794 .gpo.gpo0_enable = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpo1_enable, 0), \
795 .gpo.gpo1_enable = DT_PROP_OR(DT_INST_MAX1125X(n, t), gpo1_enable, 0), \
806 /* Each data register is a 16-bit read-only register. Any attempt to write
811 * format the most negative value is 0x0000, the midscale value is 0x8000 and
812 * the most positive value is 0xFFFF. In bipolar mode if the FORMAT
814 * bit= ‘0’, then the data format is two’s complement. In two’s
815 * complement the negative full-scale value is 0x8000, the midscale is 0x0000
816 * and the positive full scale is 0x7FFF. Any input exceeding the available
822 /* Each data register is a 24-bit read-only register. Any attempt to write
827 * the most negative value is 0x000000, the midscale value is 0x800000 and
828 * the most positive value is 0xFFFFFF. In bipolar mode if the FORMAT
829 * bit = ‘1’ then the data format is offset binary. If the FORMAT bit = ‘0’,
831 * full-scale value is 0x800000, the midscale is 0x000000 and the positive
832 * full scale is 0x7FFFFF. Any input exceeding the available input range is
852 * MAX11253: 16 bit, 6-channel, programmable gain amplifier, delta-sigma
861 * MAX1125X: 24 bit, 6-channel, programmable gain amplifier, delta-sigma