Lines Matching +full:0 +full:x00 +full:- +full:positive
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/adc/ads114s0x_adc.h>
36 #define ADS114S0X_VBIAS_PIN_MIN 0
51 ADS114S0X_COMMAND_NOP = 0x00,
52 ADS114S0X_COMMAND_WAKEUP = 0x02,
53 ADS114S0X_COMMAND_POWERDOWN = 0x04,
54 ADS114S0X_COMMAND_RESET = 0x06,
55 ADS114S0X_COMMAND_START = 0x08,
56 ADS114S0X_COMMAND_STOP = 0x0A,
57 ADS114S0X_COMMAND_SYOCAL = 0x16,
58 ADS114S0X_COMMAND_SYGCAL = 0x17,
59 ADS114S0X_COMMAND_SFOCAL = 0x19,
60 ADS114S0X_COMMAND_RDATA = 0x12,
61 ADS114S0X_COMMAND_RREG = 0x20,
62 ADS114S0X_COMMAND_WREG = 0x40,
66 ADS114S0X_REGISTER_ID = 0x00,
67 ADS114S0X_REGISTER_STATUS = 0x01,
68 ADS114S0X_REGISTER_INPMUX = 0x02,
69 ADS114S0X_REGISTER_PGA = 0x03,
70 ADS114S0X_REGISTER_DATARATE = 0x04,
71 ADS114S0X_REGISTER_REF = 0x05,
72 ADS114S0X_REGISTER_IDACMAG = 0x06,
73 ADS114S0X_REGISTER_IDACMUX = 0x07,
74 ADS114S0X_REGISTER_VBIAS = 0x08,
75 ADS114S0X_REGISTER_SYS = 0x09,
76 ADS114S0X_REGISTER_OFCAL0 = 0x0B,
77 ADS114S0X_REGISTER_OFCAL1 = 0x0C,
78 ADS114S0X_REGISTER_FSCAL0 = 0x0E,
79 ADS114S0X_REGISTER_FSCAL1 = 0x0F,
80 ADS114S0X_REGISTER_GPIODAT = 0x10,
81 ADS114S0X_REGISTER_GPIOCON = 0x11,
85 FIELD_GET(GENMASK(pos + length - 1, pos), value)
87 target &= ~GENMASK(pos + length - 1, pos); \
88 target |= FIELD_PREP(GENMASK(pos + length - 1, pos), value)
91 #define ADS114S0X_REGISTER_ID_DEV_ID_POS 0
155 #define ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS 0
171 #define ADS114S0X_REGISTER_INPMUX_MUXN_POS 0
195 #define ADS114S0X_REGISTER_PGA_GAIN_POS 0
235 #define ADS114S0X_REGISTER_DATARATE_DR_POS 0
275 #define ADS114S0X_REGISTER_REF_REFCON_POS 0
299 #define ADS114S0X_REGISTER_IDACMAG_IMAG_POS 0
315 #define ADS114S0X_REGISTER_IDACMUX_I1MUX_POS 0
339 #define ADS114S0X_REGISTER_GPIODAT_DAT_POS 0
347 #define ADS114S0X_REGISTER_GPIOCON_CON_POS 0
356 * - AIN0 as positive input
357 * - AIN1 as negative input
360 ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, 0b0000); \
361 ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, 0b0001)
363 * - disable reference monitor
364 * - enable positive reference buffer
365 * - disable negative reference buffer
366 * - use internal reference
367 * - enable internal voltage reference
370 ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, 0b00); \
371 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, 0b0); \
372 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, 0b1); \
373 ADS114S0X_REGISTER_REF_REFSEL_SET(target, 0b10); \
374 ADS114S0X_REGISTER_REF_REFCON_SET(target, 0b01)
376 * - disable global chop
377 * - use internal oscillator
378 * - single shot conversion mode
379 * - low latency filter
380 * - 20 samples per second
383 ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, 0b0); \
384 ADS114S0X_REGISTER_DATARATE_CLK_SET(target, 0b0); \
385 ADS114S0X_REGISTER_DATARATE_MODE_SET(target, 0b1); \
386 ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, 0b1); \
387 ADS114S0X_REGISTER_DATARATE_DR_SET(target, 0b0100)
389 * - delay of 14*t_mod
390 * - disable gain
391 * - gain 1
394 ADS114S0X_REGISTER_PGA_DELAY_SET(target, 0b000); \
395 ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, 0b00); \
396 ADS114S0X_REGISTER_PGA_GAIN_SET(target, 0b000)
398 * - disable PGA output rail flag
399 * - low-side power switch
400 * - IDAC off
403 ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, 0b0); \
404 ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, 0b0); \
405 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, 0b0000)
407 * - disconnect IDAC1
408 * - disconnect IDAC2
411 ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, 0b1111); \
412 ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, 0b1111)
453 k_sem_give(&data->data_ready_signal); in ads114s0x_data_ready_handler()
459 const struct ads114s0x_config *config = dev->config; in ads114s0x_read_register()
479 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_RREG) | ((uint8_t)register_address); in ads114s0x_read_register()
481 buffer_tx[1] = 0x00; in ads114s0x_read_register()
483 int result = spi_transceive_dt(&config->bus, &tx, &rx); in ads114s0x_read_register()
485 if (result != 0) { in ads114s0x_read_register()
486 LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result); in ads114s0x_read_register()
491 LOG_DBG("%s: read from register 0x%02X value 0x%02X", dev->name, register_address, *value); in ads114s0x_read_register()
493 return 0; in ads114s0x_read_register()
499 const struct ads114s0x_config *config = dev->config; in ads114s0x_write_register()
510 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_address); in ads114s0x_write_register()
512 buffer_tx[1] = 0x00; in ads114s0x_write_register()
515 LOG_DBG("%s: writing to register 0x%02X value 0x%02X", dev->name, register_address, value); in ads114s0x_write_register()
516 int result = spi_write_dt(&config->bus, &tx); in ads114s0x_write_register()
518 if (result != 0) { in ads114s0x_write_register()
519 LOG_ERR("%s: spi_write failed with error %i", dev->name, result); in ads114s0x_write_register()
523 return 0; in ads114s0x_write_register()
530 const struct ads114s0x_config *config = dev->config; in ads114s0x_write_multiple_registers()
547 if (count == 0) { in ads114s0x_write_multiple_registers()
548 LOG_WRN("%s: ignoring the command to write 0 registers", dev->name); in ads114s0x_write_multiple_registers()
549 return -EINVAL; in ads114s0x_write_multiple_registers()
552 buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_addresses[0]); in ads114s0x_write_multiple_registers()
553 buffer_tx[1] = count - 1; in ads114s0x_write_multiple_registers()
560 __ASSERT(register_addresses[i - 1] + 1 == register_addresses[i], in ads114s0x_write_multiple_registers()
564 int result = spi_write_dt(&config->bus, &tx); in ads114s0x_write_multiple_registers()
566 if (result != 0) { in ads114s0x_write_multiple_registers()
567 LOG_ERR("%s: spi_write failed with error %i", dev->name, result); in ads114s0x_write_multiple_registers()
571 return 0; in ads114s0x_write_multiple_registers()
576 const struct ads114s0x_config *config = dev->config; in ads114s0x_send_command()
587 buffer_tx[0] = (uint8_t)command; in ads114s0x_send_command()
589 LOG_DBG("%s: sending command 0x%02X", dev->name, command); in ads114s0x_send_command()
590 int result = spi_write_dt(&config->bus, &tx); in ads114s0x_send_command()
592 if (result != 0) { in ads114s0x_send_command()
593 LOG_ERR("%s: spi_write failed with error %i", dev->name, result); in ads114s0x_send_command()
597 return 0; in ads114s0x_send_command()
603 const struct ads114s0x_config *config = dev->config; in ads114s0x_channel_setup()
604 uint8_t input_mux = 0; in ads114s0x_channel_setup()
605 uint8_t reference_control = 0; in ads114s0x_channel_setup()
606 uint8_t data_rate = 0; in ads114s0x_channel_setup()
607 uint8_t gain = 0; in ads114s0x_channel_setup()
608 uint8_t idac_magnitude = 0; in ads114s0x_channel_setup()
609 uint8_t idac_mux = 0; in ads114s0x_channel_setup()
611 uint8_t vbias = 0; in ads114s0x_channel_setup()
616 uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time); in ads114s0x_channel_setup()
617 uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time); in ads114s0x_channel_setup()
626 if (channel_cfg->channel_id != 0) { in ads114s0x_channel_setup()
627 LOG_ERR("%s: only one channel is supported", dev->name); in ads114s0x_channel_setup()
628 return -EINVAL; in ads114s0x_channel_setup()
636 if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT && in ads114s0x_channel_setup()
638 LOG_ERR("%s: invalid acquisition time %i", dev->name, in ads114s0x_channel_setup()
639 channel_cfg->acquisition_time); in ads114s0x_channel_setup()
640 return -EINVAL; in ads114s0x_channel_setup()
643 if (channel_cfg->acquisition_time == ADC_ACQ_TIME_DEFAULT) { in ads114s0x_channel_setup()
649 switch (channel_cfg->reference) { in ads114s0x_channel_setup()
652 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b1); in ads114s0x_channel_setup()
653 /* disable positive reference buffer */ in ads114s0x_channel_setup()
654 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b1); in ads114s0x_channel_setup()
656 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b10); in ads114s0x_channel_setup()
660 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0); in ads114s0x_channel_setup()
661 /* enable positive reference buffer */ in ads114s0x_channel_setup()
662 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0); in ads114s0x_channel_setup()
663 /* use external reference 0*/ in ads114s0x_channel_setup()
664 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b00); in ads114s0x_channel_setup()
668 ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0); in ads114s0x_channel_setup()
669 /* enable positive reference buffer */ in ads114s0x_channel_setup()
670 ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0); in ads114s0x_channel_setup()
671 /* use external reference 0*/ in ads114s0x_channel_setup()
672 ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b01); in ads114s0x_channel_setup()
675 LOG_ERR("%s: reference %i is not supported", dev->name, channel_cfg->reference); in ads114s0x_channel_setup()
676 return -EINVAL; in ads114s0x_channel_setup()
679 if (channel_cfg->differential) { in ads114s0x_channel_setup()
682 dev->name, channel_cfg->input_positive, channel_cfg->input_negative); in ads114s0x_channel_setup()
683 if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) { in ads114s0x_channel_setup()
684 LOG_ERR("%s: positive channel input %i is invalid", dev->name, in ads114s0x_channel_setup()
685 channel_cfg->input_positive); in ads114s0x_channel_setup()
686 return -EINVAL; in ads114s0x_channel_setup()
689 if (channel_cfg->input_negative >= ADS114S0X_INPUT_SELECTION_AINCOM) { in ads114s0x_channel_setup()
690 LOG_ERR("%s: negative channel input %i is invalid", dev->name, in ads114s0x_channel_setup()
691 channel_cfg->input_negative); in ads114s0x_channel_setup()
692 return -EINVAL; in ads114s0x_channel_setup()
695 if (channel_cfg->input_positive == channel_cfg->input_negative) { in ads114s0x_channel_setup()
696 LOG_ERR("%s: negative and positive channel inputs must be different", in ads114s0x_channel_setup()
697 dev->name); in ads114s0x_channel_setup()
698 return -EINVAL; in ads114s0x_channel_setup()
701 ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive); in ads114s0x_channel_setup()
702 ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, channel_cfg->input_negative); in ads114s0x_channel_setup()
703 pin_selections[0] = channel_cfg->input_positive; in ads114s0x_channel_setup()
704 pin_selections[1] = channel_cfg->input_negative; in ads114s0x_channel_setup()
707 dev->name, channel_cfg->input_positive); in ads114s0x_channel_setup()
708 if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) { in ads114s0x_channel_setup()
709 LOG_ERR("%s: channel input %i is invalid", dev->name, in ads114s0x_channel_setup()
710 channel_cfg->input_positive); in ads114s0x_channel_setup()
711 return -EINVAL; in ads114s0x_channel_setup()
714 ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive); in ads114s0x_channel_setup()
716 pin_selections[0] = channel_cfg->input_positive; in ads114s0x_channel_setup()
720 switch (channel_cfg->gain) { in ads114s0x_channel_setup()
723 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b000); in ads114s0x_channel_setup()
726 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b001); in ads114s0x_channel_setup()
729 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b010); in ads114s0x_channel_setup()
732 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b011); in ads114s0x_channel_setup()
735 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b100); in ads114s0x_channel_setup()
738 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b101); in ads114s0x_channel_setup()
741 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b110); in ads114s0x_channel_setup()
744 ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b111); in ads114s0x_channel_setup()
747 LOG_ERR("%s: gain value %i not supported", dev->name, channel_cfg->gain); in ads114s0x_channel_setup()
748 return -EINVAL; in ads114s0x_channel_setup()
751 if (channel_cfg->gain != ADC_GAIN_1) { in ads114s0x_channel_setup()
753 ADS114S0X_REGISTER_PGA_PGA_EN_SET(gain, 0b01); in ads114s0x_channel_setup()
756 switch (config->idac_current) { in ads114s0x_channel_setup()
757 case 0: in ads114s0x_channel_setup()
758 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0000); in ads114s0x_channel_setup()
761 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0001); in ads114s0x_channel_setup()
764 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0010); in ads114s0x_channel_setup()
767 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0011); in ads114s0x_channel_setup()
770 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0100); in ads114s0x_channel_setup()
773 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0101); in ads114s0x_channel_setup()
776 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0110); in ads114s0x_channel_setup()
779 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0111); in ads114s0x_channel_setup()
782 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1000); in ads114s0x_channel_setup()
785 ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1001); in ads114s0x_channel_setup()
788 LOG_ERR("%s: IDAC magnitude %i not supported", dev->name, config->idac_current); in ads114s0x_channel_setup()
789 return -EINVAL; in ads114s0x_channel_setup()
792 if (channel_cfg->current_source_pin_set) { in ads114s0x_channel_setup()
793 LOG_DBG("%s: current source pin set to %i and %i", dev->name, in ads114s0x_channel_setup()
794 channel_cfg->current_source_pin[0], channel_cfg->current_source_pin[1]); in ads114s0x_channel_setup()
795 if (channel_cfg->current_source_pin[0] > 0b1111) { in ads114s0x_channel_setup()
796 LOG_ERR("%s: invalid selection %i for I1MUX", dev->name, in ads114s0x_channel_setup()
797 channel_cfg->current_source_pin[0]); in ads114s0x_channel_setup()
798 return -EINVAL; in ads114s0x_channel_setup()
801 if (channel_cfg->current_source_pin[1] > 0b1111) { in ads114s0x_channel_setup()
802 LOG_ERR("%s: invalid selection %i for I2MUX", dev->name, in ads114s0x_channel_setup()
803 channel_cfg->current_source_pin[1]); in ads114s0x_channel_setup()
804 return -EINVAL; in ads114s0x_channel_setup()
807 ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(idac_mux, channel_cfg->current_source_pin[0]); in ads114s0x_channel_setup()
808 ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(idac_mux, channel_cfg->current_source_pin[1]); in ads114s0x_channel_setup()
809 pin_selections[2] = channel_cfg->current_source_pin[0]; in ads114s0x_channel_setup()
810 pin_selections[3] = channel_cfg->current_source_pin[1]; in ads114s0x_channel_setup()
813 LOG_DBG("%s: current source pins not set", dev->name); in ads114s0x_channel_setup()
817 for (size_t i = 0; i < pin_selections_size; ++i) { in ads114s0x_channel_setup()
829 dev->name); in ads114s0x_channel_setup()
830 return -EINVAL; in ads114s0x_channel_setup()
835 ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(vbias, config->vbias_level); in ads114s0x_channel_setup()
837 if ((channel_cfg->vbias_pins & in ads114s0x_channel_setup()
838 ~GENMASK(ADS114S0X_VBIAS_PIN_MAX, ADS114S0X_VBIAS_PIN_MIN)) != 0) { in ads114s0x_channel_setup()
839 LOG_ERR("%s: invalid VBIAS pin selection 0x%08X", dev->name, in ads114s0x_channel_setup()
840 channel_cfg->vbias_pins); in ads114s0x_channel_setup()
841 return -EINVAL; in ads114s0x_channel_setup()
844 vbias |= channel_cfg->vbias_pins; in ads114s0x_channel_setup()
846 register_addresses[0] = ADS114S0X_REGISTER_INPMUX; in ads114s0x_channel_setup()
854 values[0] = input_mux; in ads114s0x_channel_setup()
866 if (result != 0) { in ads114s0x_channel_setup()
867 LOG_ERR("%s: unable to configure registers", dev->name); in ads114s0x_channel_setup()
871 return 0; in ads114s0x_channel_setup()
878 if (sequence->options) { in ads114s0x_validate_buffer_size()
879 needed *= (1 + sequence->options->extra_samplings); in ads114s0x_validate_buffer_size()
882 if (sequence->buffer_size < needed) { in ads114s0x_validate_buffer_size()
883 return -ENOMEM; in ads114s0x_validate_buffer_size()
886 return 0; in ads114s0x_validate_buffer_size()
892 if (sequence->resolution != ADS114S0X_RESOLUTION) { in ads114s0x_validate_sequence()
893 LOG_ERR("%s: invalid resolution", dev->name); in ads114s0x_validate_sequence()
894 return -EINVAL; in ads114s0x_validate_sequence()
897 if (sequence->channels != BIT(0)) { in ads114s0x_validate_sequence()
898 LOG_ERR("%s: invalid channel", dev->name); in ads114s0x_validate_sequence()
899 return -EINVAL; in ads114s0x_validate_sequence()
902 if (sequence->oversampling) { in ads114s0x_validate_sequence()
903 LOG_ERR("%s: oversampling is not supported", dev->name); in ads114s0x_validate_sequence()
904 return -EINVAL; in ads114s0x_validate_sequence()
915 data->buffer = data->buffer_ptr; in adc_context_update_buffer_pointer()
923 data->buffer_ptr = data->buffer; in adc_context_start_sampling()
924 k_sem_give(&data->acquire_signal); in adc_context_start_sampling()
931 struct ads114s0x_data *data = dev->data; in ads114s0x_adc_start_read()
935 if (result != 0) { in ads114s0x_adc_start_read()
936 LOG_ERR("%s: sequence validation failed", dev->name); in ads114s0x_adc_start_read()
940 data->buffer = sequence->buffer; in ads114s0x_adc_start_read()
942 adc_context_start_read(&data->ctx, sequence); in ads114s0x_adc_start_read()
945 result = adc_context_wait_for_completion(&data->ctx); in ads114s0x_adc_start_read()
953 const struct ads114s0x_config *config = dev->config; in ads114s0x_send_start_read()
956 if (config->gpio_start_sync.port == 0) { in ads114s0x_send_start_read()
958 if (result != 0) { in ads114s0x_send_start_read()
959 LOG_ERR("%s: unable to send START/SYNC command", dev->name); in ads114s0x_send_start_read()
963 result = gpio_pin_set_dt(&config->gpio_start_sync, 1); in ads114s0x_send_start_read()
965 if (result != 0) { in ads114s0x_send_start_read()
966 LOG_ERR("%s: unable to start ADC operation", dev->name); in ads114s0x_send_start_read()
973 result = gpio_pin_set_dt(&config->gpio_start_sync, 0); in ads114s0x_send_start_read()
975 if (result != 0) { in ads114s0x_send_start_read()
976 LOG_ERR("%s: unable to start ADC operation", dev->name); in ads114s0x_send_start_read()
981 return 0; in ads114s0x_send_start_read()
986 struct ads114s0x_data *data = dev->data; in ads114s0x_wait_data_ready()
988 return k_sem_take(&data->data_ready_signal, ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT); in ads114s0x_wait_data_ready()
993 const struct ads114s0x_config *config = dev->config; in ads114s0x_read_sample()
1013 buffer_tx[0] = (uint8_t)ADS114S0X_COMMAND_RDATA; in ads114s0x_read_sample()
1015 int result = spi_transceive_dt(&config->bus, &tx, &rx); in ads114s0x_read_sample()
1017 if (result != 0) { in ads114s0x_read_sample()
1018 LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result); in ads114s0x_read_sample()
1023 LOG_DBG("%s: read ADC sample %i", dev->name, *buffer); in ads114s0x_read_sample()
1025 return 0; in ads114s0x_read_sample()
1031 struct ads114s0x_data *data = dev->data; in ads114s0x_adc_perform_read()
1033 k_sem_take(&data->acquire_signal, K_FOREVER); in ads114s0x_adc_perform_read()
1034 k_sem_reset(&data->data_ready_signal); in ads114s0x_adc_perform_read()
1037 if (result != 0) { in ads114s0x_adc_perform_read()
1038 LOG_ERR("%s: unable to start ADC conversion", dev->name); in ads114s0x_adc_perform_read()
1039 adc_context_complete(&data->ctx, result); in ads114s0x_adc_perform_read()
1044 if (result != 0) { in ads114s0x_adc_perform_read()
1045 LOG_ERR("%s: waiting for data to be ready failed", dev->name); in ads114s0x_adc_perform_read()
1046 adc_context_complete(&data->ctx, result); in ads114s0x_adc_perform_read()
1050 result = ads114s0x_read_sample(dev, data->buffer); in ads114s0x_adc_perform_read()
1051 if (result != 0) { in ads114s0x_adc_perform_read()
1052 LOG_ERR("%s: reading sample failed", dev->name); in ads114s0x_adc_perform_read()
1053 adc_context_complete(&data->ctx, result); in ads114s0x_adc_perform_read()
1057 data->buffer++; in ads114s0x_adc_perform_read()
1059 adc_context_on_sampling_done(&data->ctx, dev); in ads114s0x_adc_perform_read()
1069 struct ads114s0x_data *data = dev->data; in ads114s0x_adc_read_async()
1071 adc_context_lock(&data->ctx, true, async); in ads114s0x_adc_read_async()
1073 adc_context_release(&data->ctx, result); in ads114s0x_adc_read_async()
1081 struct ads114s0x_data *data = dev->data; in ads114s0x_read()
1083 adc_context_lock(&data->ctx, false, NULL); in ads114s0x_read()
1085 adc_context_release(&data->ctx, result); in ads114s0x_read()
1094 struct ads114s0x_data *data = dev->data; in ads114s0x_read()
1096 adc_context_lock(&data->ctx, false, NULL); in ads114s0x_read()
1099 while (result == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) { in ads114s0x_read()
1103 adc_context_release(&data->ctx, result); in ads114s0x_read()
1124 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_write_config()
1127 uint8_t gpio_dat = 0; in ads114s0x_gpio_write_config()
1128 uint8_t gpio_con = 0; in ads114s0x_gpio_write_config()
1130 ADS114S0X_REGISTER_GPIOCON_CON_SET(gpio_con, data->gpio_enabled); in ads114s0x_gpio_write_config()
1131 ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value); in ads114s0x_gpio_write_config()
1132 ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction); in ads114s0x_gpio_write_config()
1134 register_values[0] = gpio_dat; in ads114s0x_gpio_write_config()
1136 register_addresses[0] = ADS114S0X_REGISTER_GPIODAT; in ads114s0x_gpio_write_config()
1144 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_write_value()
1145 uint8_t gpio_dat = 0; in ads114s0x_gpio_write_value()
1147 ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value); in ads114s0x_gpio_write_value()
1148 ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction); in ads114s0x_gpio_write_value()
1155 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_set_output()
1156 int result = 0; in ads114s0x_gpio_set_output()
1159 LOG_ERR("%s: invalid pin %i", dev->name, pin); in ads114s0x_gpio_set_output()
1160 return -EINVAL; in ads114s0x_gpio_set_output()
1163 k_mutex_lock(&data->gpio_lock, K_FOREVER); in ads114s0x_gpio_set_output()
1165 data->gpio_enabled |= BIT(pin); in ads114s0x_gpio_set_output()
1166 data->gpio_direction &= ~BIT(pin); in ads114s0x_gpio_set_output()
1169 data->gpio_value |= BIT(pin); in ads114s0x_gpio_set_output()
1171 data->gpio_value &= ~BIT(pin); in ads114s0x_gpio_set_output()
1176 k_mutex_unlock(&data->gpio_lock); in ads114s0x_gpio_set_output()
1183 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_set_input()
1184 int result = 0; in ads114s0x_gpio_set_input()
1187 LOG_ERR("%s: invalid pin %i", dev->name, pin); in ads114s0x_gpio_set_input()
1188 return -EINVAL; in ads114s0x_gpio_set_input()
1191 k_mutex_lock(&data->gpio_lock, K_FOREVER); in ads114s0x_gpio_set_input()
1193 data->gpio_enabled |= BIT(pin); in ads114s0x_gpio_set_input()
1194 data->gpio_direction |= BIT(pin); in ads114s0x_gpio_set_input()
1195 data->gpio_value &= ~BIT(pin); in ads114s0x_gpio_set_input()
1199 k_mutex_unlock(&data->gpio_lock); in ads114s0x_gpio_set_input()
1206 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_deconfigure()
1207 int result = 0; in ads114s0x_gpio_deconfigure()
1210 LOG_ERR("%s: invalid pin %i", dev->name, pin); in ads114s0x_gpio_deconfigure()
1211 return -EINVAL; in ads114s0x_gpio_deconfigure()
1214 k_mutex_lock(&data->gpio_lock, K_FOREVER); in ads114s0x_gpio_deconfigure()
1216 data->gpio_enabled &= ~BIT(pin); in ads114s0x_gpio_deconfigure()
1217 data->gpio_direction |= BIT(pin); in ads114s0x_gpio_deconfigure()
1218 data->gpio_value &= ~BIT(pin); in ads114s0x_gpio_deconfigure()
1222 k_mutex_unlock(&data->gpio_lock); in ads114s0x_gpio_deconfigure()
1229 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_set_pin_value()
1230 int result = 0; in ads114s0x_gpio_set_pin_value()
1233 LOG_ERR("%s: invalid pin %i", dev->name, pin); in ads114s0x_gpio_set_pin_value()
1234 return -EINVAL; in ads114s0x_gpio_set_pin_value()
1237 k_mutex_lock(&data->gpio_lock, K_FOREVER); in ads114s0x_gpio_set_pin_value()
1239 if ((BIT(pin) & data->gpio_enabled) == 0) { in ads114s0x_gpio_set_pin_value()
1240 LOG_ERR("%s: gpio pin %i not configured", dev->name, pin); in ads114s0x_gpio_set_pin_value()
1241 result = -EINVAL; in ads114s0x_gpio_set_pin_value()
1242 } else if ((BIT(pin) & data->gpio_direction) != 0) { in ads114s0x_gpio_set_pin_value()
1243 LOG_ERR("%s: gpio pin %i not configured as output", dev->name, pin); in ads114s0x_gpio_set_pin_value()
1244 result = -EINVAL; in ads114s0x_gpio_set_pin_value()
1246 data->gpio_value |= BIT(pin); in ads114s0x_gpio_set_pin_value()
1251 k_mutex_unlock(&data->gpio_lock); in ads114s0x_gpio_set_pin_value()
1258 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_get_pin_value()
1259 int result = 0; in ads114s0x_gpio_get_pin_value()
1263 LOG_ERR("%s: invalid pin %i", dev->name, pin); in ads114s0x_gpio_get_pin_value()
1264 return -EINVAL; in ads114s0x_gpio_get_pin_value()
1267 k_mutex_lock(&data->gpio_lock, K_FOREVER); in ads114s0x_gpio_get_pin_value()
1269 if ((BIT(pin) & data->gpio_enabled) == 0) { in ads114s0x_gpio_get_pin_value()
1270 LOG_ERR("%s: gpio pin %i not configured", dev->name, pin); in ads114s0x_gpio_get_pin_value()
1271 result = -EINVAL; in ads114s0x_gpio_get_pin_value()
1272 } else if ((BIT(pin) & data->gpio_direction) == 0) { in ads114s0x_gpio_get_pin_value()
1273 LOG_ERR("%s: gpio pin %i not configured as input", dev->name, pin); in ads114s0x_gpio_get_pin_value()
1274 result = -EINVAL; in ads114s0x_gpio_get_pin_value()
1277 data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat); in ads114s0x_gpio_get_pin_value()
1278 *value = (BIT(pin) & data->gpio_value) != 0; in ads114s0x_gpio_get_pin_value()
1281 k_mutex_unlock(&data->gpio_lock); in ads114s0x_gpio_get_pin_value()
1288 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_port_get_raw()
1289 int result = 0; in ads114s0x_gpio_port_get_raw()
1292 k_mutex_lock(&data->gpio_lock, K_FOREVER); in ads114s0x_gpio_port_get_raw()
1295 data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat); in ads114s0x_gpio_port_get_raw()
1296 *value = data->gpio_value; in ads114s0x_gpio_port_get_raw()
1298 k_mutex_unlock(&data->gpio_lock); in ads114s0x_gpio_port_get_raw()
1306 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_port_set_masked_raw()
1307 int result = 0; in ads114s0x_gpio_port_set_masked_raw()
1309 k_mutex_lock(&data->gpio_lock, K_FOREVER); in ads114s0x_gpio_port_set_masked_raw()
1311 data->gpio_value = ((data->gpio_value & ~mask) | (mask & value)) & data->gpio_enabled & in ads114s0x_gpio_port_set_masked_raw()
1312 ~data->gpio_direction; in ads114s0x_gpio_port_set_masked_raw()
1315 k_mutex_unlock(&data->gpio_lock); in ads114s0x_gpio_port_set_masked_raw()
1322 struct ads114s0x_data *data = dev->data; in ads114s0x_gpio_port_toggle_bits()
1323 int result = 0; in ads114s0x_gpio_port_toggle_bits()
1325 k_mutex_lock(&data->gpio_lock, K_FOREVER); in ads114s0x_gpio_port_toggle_bits()
1327 data->gpio_value = (data->gpio_value ^ pins) & data->gpio_enabled & ~data->gpio_direction; in ads114s0x_gpio_port_toggle_bits()
1330 k_mutex_unlock(&data->gpio_lock); in ads114s0x_gpio_port_toggle_bits()
1339 uint8_t status = 0; in ads114s0x_init()
1340 uint8_t reference_control = 0; in ads114s0x_init()
1343 const struct ads114s0x_config *config = dev->config; in ads114s0x_init()
1344 struct ads114s0x_data *data = dev->data; in ads114s0x_init()
1346 adc_context_init(&data->ctx); in ads114s0x_init()
1348 k_sem_init(&data->data_ready_signal, 0, 1); in ads114s0x_init()
1349 k_sem_init(&data->acquire_signal, 0, 1); in ads114s0x_init()
1352 k_mutex_init(&data->gpio_lock); in ads114s0x_init()
1355 if (!spi_is_ready_dt(&config->bus)) { in ads114s0x_init()
1356 LOG_ERR("%s: SPI device is not ready", dev->name); in ads114s0x_init()
1357 return -ENODEV; in ads114s0x_init()
1360 if (config->gpio_reset.port != NULL) { in ads114s0x_init()
1361 result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE); in ads114s0x_init()
1362 if (result != 0) { in ads114s0x_init()
1363 LOG_ERR("%s: failed to initialize GPIO for reset", dev->name); in ads114s0x_init()
1368 if (config->gpio_start_sync.port != NULL) { in ads114s0x_init()
1369 result = gpio_pin_configure_dt(&config->gpio_start_sync, GPIO_OUTPUT_INACTIVE); in ads114s0x_init()
1370 if (result != 0) { in ads114s0x_init()
1371 LOG_ERR("%s: failed to initialize GPIO for start/sync", dev->name); in ads114s0x_init()
1376 result = gpio_pin_configure_dt(&config->gpio_data_ready, GPIO_INPUT); in ads114s0x_init()
1377 if (result != 0) { in ads114s0x_init()
1378 LOG_ERR("%s: failed to initialize GPIO for data ready", dev->name); in ads114s0x_init()
1382 result = gpio_pin_interrupt_configure_dt(&config->gpio_data_ready, GPIO_INT_EDGE_TO_ACTIVE); in ads114s0x_init()
1383 if (result != 0) { in ads114s0x_init()
1384 LOG_ERR("%s: failed to configure data ready interrupt", dev->name); in ads114s0x_init()
1385 return -EIO; in ads114s0x_init()
1388 gpio_init_callback(&data->callback_data_ready, ads114s0x_data_ready_handler, in ads114s0x_init()
1389 BIT(config->gpio_data_ready.pin)); in ads114s0x_init()
1390 result = gpio_add_callback(config->gpio_data_ready.port, &data->callback_data_ready); in ads114s0x_init()
1391 if (result != 0) { in ads114s0x_init()
1392 LOG_ERR("%s: failed to add data ready callback", dev->name); in ads114s0x_init()
1393 return -EIO; in ads114s0x_init()
1397 k_tid_t tid = k_thread_create(&data->thread, config->stack, in ads114s0x_init()
1400 CONFIG_ADC_ADS114S0X_ASYNC_THREAD_INIT_PRIO, 0, K_NO_WAIT); in ads114s0x_init()
1406 if (config->gpio_reset.port == NULL) { in ads114s0x_init()
1408 if (result != 0) { in ads114s0x_init()
1409 LOG_ERR("%s: unable to send RESET command", dev->name); in ads114s0x_init()
1414 gpio_pin_set_dt(&config->gpio_reset, 0); in ads114s0x_init()
1420 if (result != 0) { in ads114s0x_init()
1421 LOG_ERR("%s: unable to read status register", dev->name); in ads114s0x_init()
1425 if (ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(status) == 0x01) { in ads114s0x_init()
1426 LOG_ERR("%s: ADS114 is not yet ready", dev->name); in ads114s0x_init()
1427 return -EBUSY; in ads114s0x_init()
1437 if (result != 0) { in ads114s0x_init()
1438 LOG_ERR("%s: unable to set default reference control values", dev->name); in ads114s0x_init()
1446 if (result != 0) { in ads114s0x_init()
1447 LOG_ERR("%s: unable to read reference control values", dev->name); in ads114s0x_init()
1452 LOG_ERR("%s: reference control register is incorrect: 0x%02X", dev->name, in ads114s0x_init()
1454 return -EIO; in ads114s0x_init()
1458 data->gpio_enabled = 0x00; in ads114s0x_init()
1459 data->gpio_direction = 0x0F; in ads114s0x_init()
1460 data->gpio_value = 0x00; in ads114s0x_init()
1464 if (result != 0) { in ads114s0x_init()
1465 LOG_ERR("%s: unable to configure defaults for GPIOs", dev->name); in ads114s0x_init()
1470 adc_context_unlock_unconditionally(&data->ctx); in ads114s0x_init()
1496 n, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
1498 .gpio_reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}), \
1500 .gpio_start_sync = GPIO_DT_SPEC_INST_GET_OR(n, start_sync_gpios, {0}), \