Lines Matching refs:ad405x_reg_update_bits
277 int ad405x_reg_update_bits(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val) in ad405x_reg_update_bits() function
530 ret = ad405x_reg_update_bits(dev, AD405X_REG_TIMER_CONFIG, AD405X_FS_BURST_AUTO_MSK, rate); in ad405x_set_sample_rate()
552 ret = ad405x_reg_update_bits(dev, AD405X_REG_AVG_CONFIG, AD405X_AVG_WIN_LEN_MSK, length); in ad405x_set_averaging_filter_length()
597 ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES, in ad405x_set_operation_mode()
603 ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET, in ad405x_set_operation_mode()
620 ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES, in ad405x_set_operation_mode()
626 ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET, in ad405x_set_operation_mode()
645 ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES, in ad405x_set_operation_mode()
651 ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET, in ad405x_set_operation_mode()
681 ret = ad405x_reg_update_bits(dev, AD405X_REG_GP_PIN_CONF, mask, gpx_mode_tmp); in ad405x_set_gpx_mode()
773 ret = ad405x_reg_update_bits(dev, AD405X_REG_INTERFACE_CONFIG_A, AD405X_SW_RESET_MSK, in ad405x_soft_reset()
779 return ad405x_reg_update_bits(dev, AD405X_REG_INTERFACE_CONFIG_A, AD405X_SW_RESET_MSK, 0); in ad405x_soft_reset()