Lines Matching +full:no +full:- +full:error +full:- +full:irq
24 * An **interrupt request (IRQ) signal** that triggers the ISR.
25 * A **priority level** associated with the IRQ.
31 Only a single ISR can be associated with a specific IRQ at any given time.
40 generates a fatal system error if an unexpected interrupt is signaled.
43 in mid-execution if a higher priority interrupt is signaled. The lower
62 Multi-level Interrupt Handling
65 A hardware platform can support more interrupt lines than natively-provided
75 A unique 32-bit interrupt number is assigned with information
77 Service Routine (ISR). Each interrupt level is given a byte within this 32-bit
81 .. code-block:: none
93 * '-' means interrupt line and is numbered from 0 (right most).
98 * The other LEVEL 2 controller has no nested controllers but has one
106 .. code-block:: none
108 A -> 0x00000004
109 B -> 0x00000302
110 C -> 0x00000409
111 D -> 0x00030609
117 5, that is connected to the LEVEL 1 controller's line 9 (2 -> 5 -> 9).
125 prevent ISRs from executing while it is performing time-sensitive
128 A thread may temporarily prevent all IRQ handling in the system using
129 an **IRQ lock**. This lock can be applied even when it is already in effect,
131 The thread must unlock its IRQ lock the same number of times it was locked
136 The IRQ lock is thread-specific. If thread A locks out interrupts
138 for N milliseconds), the thread's IRQ lock no longer applies once
144 IRQ lock. (Whether interrupts can be processed while the kernel is
145 switching between two threads that are using the IRQ lock is
146 architecture-specific.)
149 re-establishes thread A's IRQ lock. This ensures thread A won't be
150 interrupted until it has explicitly unlocked its IRQ lock.
152 If thread A does not sleep but does make a higher-priority thread B
153 ready, the IRQ lock will inhibit any preemption that would otherwise
155 <scheduling_v2>` reached after releasing the IRQ lock.
157 Alternatively, a thread may temporarily **disable** a specified IRQ
158 so its associated ISR does not execute when the IRQ is signaled.
159 The IRQ must be subsequently **enabled** to permit the ISR to execute.
162 Disabling an IRQ prevents *all* threads in the system from being preempted
163 by the associated ISR, not just the thread that disabled the IRQ.
166 -----------------------
168 Preventing interruptions by applying an IRQ lock may increase the observed
170 for certain low-latency use-cases.
172 The kernel addresses such use-cases by allowing interrupts with critical
175 *zero-latency interrupts*. The support for zero-latency interrupts requires
181 Zero-latency interrupts are expected to be used to manage hardware events
184 APIs inside a zero-latency interrupt context is responsible for directly
185 verifying correct behavior). Zero-latency interrupts may not modify any data
190 Zero-latency interrupts are supported on an architecture-specific basis.
191 The feature is currently implemented in the ARM Cortex-M architecture
202 The kernel supports several mechanisms for offloading interrupt-related
205 * An ISR can signal a helper thread to do interrupt-related processing
212 switch to that thread when the ISR completes, allowing interrupt-related
215 the currently executing cooperative thread or other higher-priority threads
245 register gets triggered, the ISR will no longer get invoked.
248 result in a non-negligible increase in the binary size. Use with caution.
262 Drivers that have multiple instances may need to define per-instance
267 .. code-block:: c
269 #define MY_DEV_IRQ 24 /* device uses IRQ 24 */
273 #define MY_IRQ_FLAGS 0 /* IRQ flags */
294 .. code-block:: c
306 be enabled. Removing or re-configuring a dynamic interrupt is currently
313 for some low-latency use-cases. Specifically:
318 will be resumed from low-power state before the ISR is executed, which can be
319 very time-consuming
327 Zephyr supports so-called 'direct' interrupts, which are installed via
334 .. code-block:: c
336 #define MY_DEV_IRQ 24 /* device uses IRQ 24 */
339 #define MY_IRQ_FLAGS 0 /* IRQ flags */
357 architecture-specific basis. (The feature is currently implemented in
358 ARM Cortex-M architecture variant. Dynamic direct interrupts feature is
359 exposed to the user via an ARM-only API.)
366 .. code-block:: c
374 #define MY_IRQ_FLAGS 0 /* IRQ flags */
396 code will generate a build error. Otherwise, the above code will result in the two ISRs
400 (current number of clients), a build error will be generated.
412 .. code-block:: c
420 #define MY_IRQ_FLAGS 0 /* IRQ flags */
451 error will be generated.
474 is no longer pointing to the function that was expected.
488 -----------------------------
495 .. code-block:: c
498 /** IRQ line number */
499 int32_t irq;
500 /** Flags for this IRQ, see ISR_FLAG_* definitions */
504 /** Parameter for non-direct IRQs */
512 .. code-block:: c
519 struct _isr_list isrs[]; <- of size num_isrs
538 array of function pointers, where each element n corresponds to the IRQ handler
539 for IRQ line n, and the function pointers are:
544 of the common software IRQ handler is placed here. This code does common
548 spurious IRQ handler will be placed here. The spurious IRQ handler
549 causes a system fatal error if encountered.
565 .. code-block:: c
572 This is used by the common software IRQ handler to look up the ISR and its
573 argument and execute it. The active IRQ line is looked up in an interrupt
581 .. code-block:: c
594 ----------------------------------
610 .. code-block:: c
613 /** IRQ line number */
614 int32_t irq;
615 /** Flags for this IRQ, see ISR_FLAG_* definitions */
630 .. code-block:: c
642 .. code-block:: c
648 .. code-block:: c
676 -----------
681 :ref:`gen_idt.py` tool uses the .intList section to create it. However, on APIC-based
682 systems the indexes in the vector table do not correspond to the IRQ line. The
685 scheme, interrupts of priority level 0 will be placed in vectors 32-47, level 1
686 48-63, and so forth. When the :ref:`gen_idt.py` tool is constructing the IDT, when it
691 no foolproof way to determine which vector was fired, so a software ISR table
692 indexed by IRQ line is not used. Instead, the :c:macro:`IRQ_CONNECT` call
701 runtime what vector is associated with an IRQ line. :ref:`gen_idt.py` additionally
702 creates an _irq_to_interrupt_vector array which maps an IRQ line to its
704 to program the IRQ-to-vector association in the interrupt controller.
706 For dynamic interrupts, the build must generate some 4-byte dynamic interrupt
714 -------------------------------------------------------
716 When generating interrupts in the multi-level configuration, 8-bits per level is the default
721 the total bits used between all levels must sum to be less than or equal to 32-bits,
722 fitting into a single 32-bit integer. To modify the bit total per level, override the
748 Additional architecture-specific and device-specific configuration options