Lines Matching +full:high +full:- +full:dynamic +full:- +full:output
43 in mid-execution if a higher priority interrupt is signaled. The lower
62 Multi-level Interrupt Handling
65 A hardware platform can support more interrupt lines than natively-provided
75 A unique 32-bit interrupt number is assigned with information
77 Service Routine (ISR). Each interrupt level is given a byte within this 32-bit
81 .. code-block:: none
93 * '-' means interrupt line and is numbered from 0 (right most).
106 .. code-block:: none
108 A -> 0x00000004
109 B -> 0x00000302
110 C -> 0x00000409
111 D -> 0x00030609
117 5, that is connected to the LEVEL 1 controller's line 9 (2 -> 5 -> 9).
125 prevent ISRs from executing while it is performing time-sensitive
136 The IRQ lock is thread-specific. If thread A locks out interrupts
146 architecture-specific.)
149 re-establishes thread A's IRQ lock. This ensures thread A won't be
152 If thread A does not sleep but does make a higher-priority thread B
166 -----------------------
169 interrupt latency. A high interrupt latency, however, may not be acceptable
170 for certain low-latency use-cases.
172 The kernel addresses such use-cases by allowing interrupts with critical
175 *zero-latency interrupts*. The support for zero-latency interrupts requires
181 Zero-latency interrupts are expected to be used to manage hardware events
184 APIs inside a zero-latency interrupt context is responsible for directly
185 verifying correct behavior). Zero-latency interrupts may not modify any data
190 Zero-latency interrupts are supported on an architecture-specific basis.
191 The feature is currently implemented in the ARM Cortex-M architecture
202 The kernel supports several mechanisms for offloading interrupt-related
205 * An ISR can signal a helper thread to do interrupt-related processing
212 switch to that thread when the ISR completes, allowing interrupt-related
215 the currently executing cooperative thread or other higher-priority threads
242 Enabling the shared interrupt support and dynamic interrupt support will
248 result in a non-negligible increase in the binary size. Use with caution.
262 Drivers that have multiple instances may need to define per-instance
267 .. code-block:: c
294 .. code-block:: c
305 Dynamic interrupts require the :kconfig:option:`CONFIG_DYNAMIC_INTERRUPTS` option to
306 be enabled. Removing or re-configuring a dynamic interrupt is currently
313 for some low-latency use-cases. Specifically:
318 will be resumed from low-power state before the ISR is executed, which can be
319 very time-consuming
327 Zephyr supports so-called 'direct' interrupts, which are installed via
334 .. code-block:: c
356 Installation of dynamic direct interrupts is supported on an
357 architecture-specific basis. (The feature is currently implemented in
358 ARM Cortex-M architecture variant. Dynamic direct interrupts feature is
359 exposed to the user via an ARM-only API.)
366 .. code-block:: c
402 If dynamic interrupts are enabled, :c:func:`irq_connect_dynamic` will allow sharing interrupts
412 .. code-block:: c
466 and produce the required output.
488 -----------------------------
495 .. code-block:: c
504 /** Parameter for non-direct IRQs */
512 .. code-block:: c
519 struct _isr_list isrs[]; <- of size num_isrs
565 .. code-block:: c
581 .. code-block:: c
594 ----------------------------------
610 .. code-block:: c
630 .. code-block:: c
642 .. code-block:: c
648 .. code-block:: c
676 -----------
681 :ref:`gen_idt.py` tool uses the .intList section to create it. However, on APIC-based
685 scheme, interrupts of priority level 0 will be placed in vectors 32-47, level 1
686 48-63, and so forth. When the :ref:`gen_idt.py` tool is constructing the IDT, when it
704 to program the IRQ-to-vector association in the interrupt controller.
706 For dynamic interrupts, the build must generate some 4-byte dynamic interrupt
707 stubs, one stub per dynamic interrupt in use. The number of stubs is controlled
710 and parameter out of a table populated when the dynamic interrupt was
714 -------------------------------------------------------
716 When generating interrupts in the multi-level configuration, 8-bits per level is the default
721 the total bits used between all levels must sum to be less than or equal to 32-bits,
722 fitting into a single 32-bit integer. To modify the bit total per level, override the
748 Additional architecture-specific and device-specific configuration options