Lines Matching +full:memory +full:- +full:region

15   The information here assumes that the architecture-specific MPU support is
16   enabled. See the architecture-specific documentation for details.
21   in general ensures that memory will be seen in a coherent state from multiple
27 When dealing with memory shared between a processor core and other bus masters,
30 of this, data moved into and out of memory by DMA engines will be stale in the
39 disabling caching for only a portion of memory. This can be useful when cache
42 memory at runtime.
45 ---------------------------------
58 Disabling Caching for a Memory Region
59 -------------------------------------
61 Disabling caching for only a portion of memory can be a good performance
62 compromise if performance on the uncached memory is not critical to the
70 * :kconfig:option:`CONFIG_MEM_ATTR`: enable the ``mem-attr`` library for
71   handling memory attributes in the device tree.
76 according to the memory attributes specified during kernel initialization. When
77 using a dedicated uncached region of memory, the linker needs to be instructed
78 to place buffers into that region. This can be accomplished by specifying the
79 memory region explicitly using ``Z_GENERIC_SECTION``:
81 .. code-block:: c
88   Configuring a distinct memory region with separate caching rules requires the
89   use of an MPU region which may be a limited resource on some architectures.
90   MPU regions may be needed by other memory protection features such as
92   or :ref:`memory domains<memory_domain>`.
95 -------------------------------------------
97 Zephyr has the ability to automatically define an uncached region in memory and
99 attribute will be placed in a special ``nocache`` linker region in memory. This
100 region will be configured as uncached by the MPU driver during initialization.
101 This is a simpler option than explicitly declaring a region of memory uncached
103 may allocate this region anywhere in RAM.
110   linker region and configure it as uncached.
114 .. code-block:: c
121   region is still a distinct MPU region even though it is automatically created
125 ---------------------
130 cacheable memory, the cache line. Data cache lines are typically 16 to 128
135 more efficient to place them in an uncached region, as unrelated data packed
139 region back to shared memory. Flush the cache associated with a buffer after the
141 region.
145   Some architectures support a cache configuration called **write-through**
147   shared memory. While this solves the cache coherence problem for CPU writes,
148   it also results in more traffic to main memory which may result in performance
152 cache lines in the specified region as stale, ensuring that the cache line will
153 be refreshed from main memory when the processor next reads from the specified
154 region. Invalidate the data cache of a buffer that a peripheral has written to
155 before reading from that region.
168 * Call :c:func:`sys_cache_data_flush_range()` to flush a memory region.
170 * Call :c:func:`sys_cache_data_invd_range()` to invalidate a memory region.
175 ---------
181 .. code-block:: c