Lines Matching +full:multi +full:- +full:image
19 There are multiple supported sub-configurations for that platform. Some but not all of currently
22 * ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
23 XY-memory
24 * ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
25 * ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options a…
26 XY-memory
27 * ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
28 * ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
29 * ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
30 * ``nsim/nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template
31 * ``nsim/nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options
32 * ``nsim/nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options
33 * ``nsim/nsim_hs5x/smp/12cores`` - SMP 12 cores 32-bit ARCv3 HS platform
34 * ``nsim/nsim_hs6x/smp/12cores`` - SMP 12 cores 64-bit ARCv3 HS platform
38 It is recommended to look at precise description of a particular sub-configuration in either
42 In case of single-core configurations it would be ``.props`` file which contains configuration
54 I.e. for the single-core ``nsim/nsim_hs5x`` platform there are
58 For the multi-core configurations there is only ``.args`` file as the multi-core configuration
61 I.e. for the multi-core ``nsim/nsim_hs5x/smp`` platform there is only
74 To run single-core Zephyr RTOS applications in simulation on this board,
77 To run multi-core Zephyr RTOS applications in simulation on this board,
80 To run Zephyr RTOS applications on FPGA-based `HAPS`_ platform,
86 Most board sub-configurations support building with both GNU and ARC MWDT toolchains, however
88 toolchains for the sub-configurations in the corresponding ``.yaml`` file.
94 * **zephyr** - implies ARC GNU toolchain from Zephyr SDK. You can find more information about
96 * **cross-compile** - implies ARC GNU cross toolchain, which is not a part of Zephyr SDK. Note that
97 some (especially new) sub-configurations may declare ``cross-compile`` toolchain support without
100 * **arcmwdt** - implies proprietary ARC MWDT toolchain. You can find more information about its
109 nSIM, for example, with the :zephyr:code-sample:`synchronization` sample:
111 .. zephyr-app-commands::
112 :zephyr-app: samples/synchronization
113 :host-os: unix
117 This will build an image with the synchronization sample app, boot it using
120 .. code-block:: console
122 *** Booting Zephyr OS build zephyr-v3.2.0-3948-gd351a024dc87 ***
137 done by passing ``-v`` flag to the west: ``west -v build -b nsim_hs samples/synchronization``
142 .. code-block:: console
144 west flash --runner mdb-hw
147 To run on HAPS, in addition to proper build and flash Zephyr image, you need setup HAPS itself
148 as well as flash proper built FPGA image (aka .bit-file). This instruction doesn't cover those
157 ------------------
163 * Allows to debug both single-core and multi-core ``nsim`` targets.
167 (regardless if single- or multi-core configuration is used):
169 .. code-block:: console
171 west debug --runner mdb-nsim
176 .. code-block:: console
178 west debug --runner mdb-hw
183 need to pass ``-v`` flag to the wrapper. For example, if you run the following command:
185 .. code-block:: console
187 west -v debug --runner mdb-nsim
192 .. code-block:: console
195 -- west debug: using runner mdb-nsim
196 …runners.mdb-nsim: mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols…
197 …runners.mdb-nsim: mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=incl…
198 runners.mdb-nsim: mdb -multifiles=core1,core0 -OKN
200 From that output it's possible to extract MDB commands used for setting-up the GUI debugging
203 .. code-block:: console
205 …mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/ze…
206 …mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=…
207 mdb -multifiles=core1,core0 -OKN
216 In case of execution or debugging with MDB on multi-core configuration on nSIM
222 ARC cores which don't share any memory regions with each other and so SMP-enabled code won't
226 ------------------
229 Debugging on nSIM via GDB is only supported on single-core configurations (which use standalone
230 nSIM). However if it's possible to launch application on multi-core nsim target that means you
232 It's the nSIM with ARC GDB restriction, real HW multi-core ARC targets can be debugged with ARC
248 .. code-block:: console
250 west debugserver --runner arc-nsim
254 * for the ARCv2 targets you should use :file:`arc-zephyr-elf-gdb`
255 * for the ARCv3 targets you should use :file:`arc64-zephyr-elf-gdb`
260 .. code-block:: console
262 arc-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf
279 reasons for that. ``.tcf`` perfectly suits building of bare-metal single-thread application -
282 The situation is completely different when multi-thread feature-rich operation system is
284 options from ``.tcf`` - but that may be far from optimal solution. For example, such approach
286 interrupts). And for DSP-enabled or for FPU-enabled systems that leads to dozens of extra
288 DSP or FPU. Instead we prefer to fine-tune the HW features usage which (with all its pros)
295 Zephyr OS configuration is defined via Kconfig and Device tree. These are non ARC-specific
309 * Options to fine-tuned MDB behavior are added (to ``.args`` files only) to disable MDB profiling
310 and fine-tune MDB behavior on multi-core systems.
315 The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim`` board
318 For the GNU toolchain the basic configuration is set via ``-mcpu`` which is defined in generic code
322 For the MWDT toolchain all hardware-specific compiler options are set directly in SoC
326 The non hardware-specific compiler options like optimizations, library selections, C / C++
333 .. target-notes::
336 .. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi