Lines Matching +full:row +full:- +full:offset
4 * SPDX-License-Identifier: Apache-2.0
12 * 32-bits, offset 0x0, This register controls mapping of the peripheral device
16 /* 32-bits, offset 0x4 */
20 * 32-bits, offset 0x8, SPI_MAP_CTRL[0] selects the mode of operation of the SPI
22 * at connector J1. Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to
27 * 32-bits, offset 0x8, This register controls the mapping of the UART signals
135 * information -> Appendix: A Hardware Functional Description -> in pmod_mux_init()
137 * + Set up pin-multiplexer of all PMOD connections in pmod_mux_init()
138 * - PM1 J1: Upper row as UART 0, lower row as SPI Slave in pmod_mux_init()
139 * - PM2 J2: IIC 0 and run/halt signals in pmod_mux_init()
140 * - PM3 J3: GPIO Port A and Port C in pmod_mux_init()
141 * - PM4 J4: IIC 1 and Port D in pmod_mux_init()
142 * - PM5 J5: Upper row as SPI Master, lower row as Port A in pmod_mux_init()
143 * - PM6 J6: Upper row as SPI Master, lower row as Port A in pmod_mux_init()