Lines Matching full:connected

21  * Slave: Normal operation, SPI_MAP_CTRL[0]=0: SPI Slave is connected to Pmod1
22  * at connector J1. Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to
65 /* Pmod1[4:1] are connected to DW GPIO Port C[11:8] */
67 /* Pmod1[4:1] are connected to DW UART0 signals */
70 /* Pmod1[10:7] are connected to DW GPIO Port A[11:8] */
72 /* Pmod1[10:7] are connected to DW SPI Slave signals */
75  * Pmod2[4:1]	 are connected to DW GPIO Port C[15:12],
76  * Pmod2[10:7] are connected to DW GPIO Port A[15:12]
82  * Pmod3[4:1]  are connected to DW GPIO Port C[19:16],
83  * Pmod3[10:7] are connected to DW GPIO Port A[19:16]
87  * Pmod3[4:3]  are connected to DW I2C signals,
88  * Pmod3[2:1]  are connected to DW GPIO Port D[1:0],
89  * Pmod3[10:7] are connected to DW GPIO Port D[3:2]
93  * Pmod4[4:1]  are connected to DW GPIO Port C[23:20],
94  * Pmod4[10:7] are connected to DW GPIO Port A[23:20]
98  * Pmod4[4:3]  are connected to DW I2C signals,
99  * Pmod4[2:1]  are connected to DW GPIO Port D[5:4],
100  * Pmod4[10:7] are connected to DW GPIO Port D[7:6]
104 /* Pmod5[4:1] are connected to DW GPIO Port C[27:24] */
106 /* Pmod5[4:1] are connected to DW SPI Master signals using CS1_N */
108 /* Pmod5[10:7] are connected to DW GPIO Port A[27:24] */
110 /* Pmod5[10:7] are connected to DW SPI Master signals using CS2_N */
113 /* Pmod6[4:1] are connected to DW GPIO Port C[31:28] */
115 /* Pmod6[4:1] are connected to DW SPI Master signals using CS0_N */
117 /* Pmod6[10:7] are connected to DW GPIO Port A[31:28] */
120  * Pmod6[8:7] are connected to the DW SPI Master chip select signals CS1_N and
121  * CS2_N, Pmod6[6:5] are connected to the ARC EM halt and sleep status signals