Lines Matching +full:0 +full:x26
37 #size-cells = <0>;
39 ssd16xx: ssd16xxfb@0 {
42 reg = <0>;
50 vcom = <0x26>;
51 border-waveform = <0x03>;
52 dummy-line = <0x30>;
53 gate-line-width = <0x0a>;
59 * n = {0,1,2...6}, each group contains
64 * For example 0x80 represents sequence VSL-VSS-VSS-VSS,
66 80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */
67 10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */
68 80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */
69 10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */
70 00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */
78 * number of Gate Pulses (length) : 3 3 0 0
94 vcom = <0x26>;
95 border-waveform = <0x01>;
96 dummy-line = <0x30>;
97 gate-line-width = <0x0a>;
104 0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */
122 pinctrl-0 = <&spi1_default>;