Lines Matching +full:flexcan +full:- +full:fd
6 The X-S32Z27X-DC (DC2) board is based on the NXP S32Z2 Real-Time Processor,
7 which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores
12 - ``s32z2xxdc2/s32z270/rtu0``, for S32Z270/RTU0
13 - ``s32z2xxdc2/s32z270/rtu1``, for S32Z270/RTU1.
19 `NXP S32Z2 Real-Time Processors website`_.
26 +-----------+------------+-------------------------------------+
29 | Arm GIC | on-chip | interrupt_controller |
30 +-----------+------------+-------------------------------------+
31 | Arm Timer | on-chip | timer |
32 +-----------+------------+-------------------------------------+
33 | LINFlexD | on-chip | serial |
34 +-----------+------------+-------------------------------------+
35 | MRU | on-chip | mbox |
36 +-----------+------------+-------------------------------------+
37 | NETC | on-chip | ethernet |
40 +-----------+------------+-------------------------------------+
41 | SIUL2 | on-chip | pinctrl |
46 +-----------+------------+-------------------------------------+
47 | SPI | on-chip | spi |
48 +-----------+------------+-------------------------------------+
49 | SWT | on-chip | watchdog |
50 +-----------+------------+-------------------------------------+
51 | CANEXCEL | on-chip | can |
52 +-----------+------------+-------------------------------------+
53 | FLEXCAN | on-chip | can |
54 +-----------+------------+-------------------------------------+
55 | SAR_ADC | on-chip | adc |
56 +-----------+------------+-------------------------------------+
57 | LPI2C | on-chip | i2c |
58 +-----------+------------+-------------------------------------+
59 | EDMA | on-chip | dma |
60 +-----------+------------+-------------------------------------+
61 | DSPI | on-chip | spi |
62 +-----------+------------+-------------------------------------+
74 +-------------------+-------------+
77 | PAD_000 - PAD_015 | PA0 - PA15 |
78 +-------------------+-------------+
79 | PAD_016 - PAD_030 | PB0 - PB14 |
80 +-------------------+-------------+
82 +-------------------+-------------+
83 | PAD_032 - PAD_047 | PD0 - PD15 |
84 +-------------------+-------------+
85 | PAD_048 - PAD_063 | PE0 - PE15 |
86 +-------------------+-------------+
87 | PAD_064 - PAD_079 | PF0 - PF15 |
88 +-------------------+-------------+
89 | PAD_080 - PAD_091 | PG0 - PG11 |
90 +-------------------+-------------+
91 | PAD_092 - PAD_095 | PH12 - PH15 |
92 +-------------------+-------------+
93 | PAD_096 - PAD_111 | PI0 - PI15 |
94 +-------------------+-------------+
95 | PAD_112 - PAD_127 | PJ0 - PJ15 |
96 +-------------------+-------------+
97 | PAD_128 - PAD_143 | PK0 - PK15 |
98 +-------------------+-------------+
99 | PAD_144 - PAD_145 | PL0 - PL1 |
100 +-------------------+-------------+
101 | PAD_146 - PAD_159 | PM2 - PM15 |
102 +-------------------+-------------+
103 | PAD_160 - PAD_169 | PN0 - PN9 |
104 +-------------------+-------------+
105 | PAD_170 - PAD_173 | PO10 - PO13 |
106 +-------------------+-------------+
109 of the samples such as :zephyr:code-sample:`blinky` or :zephyr:code-sample:`button`.
116 The Cortex-R52 cores are configured to run at 1 GHz.
122 be accessed by default on the USB micro-B connector J119.
136 cores of the system. Refer to :zephyr:code-sample:`nxp_s32_netc` to learn how to
143 --------
145 CANEXCEL supports CAN Classic (CAN 2.0) and CAN FD modes. Remote transmission
150 transceiver. Any transceiver pin-compatible with CAN 2.0 and CAN FD protocols
153 FlexCAN subsection
154 -------
156 FlexCAN supports CAN Classic (CAN 2.0) and CAN FD modes.
162 12-bit resolution. ADC channels are divided into 2 groups (precision and internal/standard).
184 - :ref:`NXP S32 Debug Probe <nxp-s32-debug-probe>` (default)
185 - :ref:`Lauterbach TRACE32 <lauterbach-trace32-debug-host-tools>`
190 Set-up the Board
198 For example, using the cross-platform `pySerial miniterm`_ terminal:
200 .. code-block:: console
202 python -m serial.tools.miniterm <port> 115200
210 You can build and debug the :zephyr:code-sample:`hello_world` sample for the board
213 .. zephyr-app-commands::
214 :zephyr-app: samples/hello_world
221 .. zephyr-app-commands::
222 :zephyr-app: samples/hello_world
231 .. code-block:: console
237 .. zephyr-app-commands::
238 :zephyr-app: samples/hello_world
240 :goals: build debug -r trace32
251 .. zephyr-app-commands::
252 :zephyr-app: samples/hello_world
254 :goals: build flash -r trace32
258 Currently, the Lauterbach start-up scripts executed with ``flash`` and
266 .. zephyr-app-commands::
267 :zephyr-app: samples/hello_world
269 :goals: build debug --tool-opt='--batch'
275 This Zephyr port can only run single core in any of the Cortex-R52 cores,
276 either in lock-step or split-lock mode. By default, Zephyr runs on the first
277 core of the RTU chosen and in lock-step mode (which is the reset
280 To build for split-lock mode, the :kconfig:option:`CONFIG_DCLS` must be
288 .. group-tab:: lockstep configuration
290 .. code-block:: console
292 west debug --core-name='R52_<rtu_id>_<core_id>_LS'
294 .. group-tab:: split-lock configuration
296 .. code-block:: console
298 west debug --core-name='R52_<rtu_id>_<core_id>'
302 - ``<rtu_id>`` is the zero-based RTU index
303 - ``<core_id>`` is the zero-based core index relative to the RTU on which to
306 For example, to build the :zephyr:code-sample:`hello_world` sample for the board
307 ``s32z2xxdc2/s32z270/rtu0`` with split-lock core configuration:
309 .. zephyr-app-commands::
310 :zephyr-app: samples/hello_world
313 :gen-args: -DCONFIG_DCLS=n
316 To execute this sample in the second core of RTU0 in split-lock mode:
318 .. code-block:: console
320 west debug --core-name='R52_0_1'
325 .. code-block:: console
327 west debug --startup-args elfFile=<elf_path> rtu=<rtu_id> core=<core_id> lockstep=<yes/no>
335 .. target-notes::
337 .. _NXP S32Z2 Real-Time Processors website:
338 …/processors-and-microcontrollers/s32-automotive-platform/s32z-and-s32e-real-time-processors/s32z2-…
341 https://pyserial.readthedocs.io/en/latest/tools.html#module-serial.tools.miniterm