2  * Copyright 2022-2023 NXP
3  * SPDX-License-Identifier: Apache-2.0
28 #define PMIC_SETTLING_TIME		2000U	/* in micro-seconds */
50 /* Core frequency levels number. */
64 /* System clock frequency. */
80 	/* Frequency exceed max supported */  in board_calc_volt_level()
84 		volt = sw1_volt[i - 1U];  in board_calc_volt_level()
128 		return -ERANGE;  in board_pmic_change_mode()
132 	if (ret != -EPERM) {  in board_pmic_change_mode()
142 /* Changes power-related config to preset profiles, like clocks and VDDCORE voltage */
168 		return -EINVAL;  in power_manager_set_profile()
172 		/* One-Time optimization after boot */  in power_manager_set_profile()
185 		CLKCTL0->SYSPLL0PFD |=	CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK |  in power_manager_set_profile()
198 		PMC->PMICCFG = 0xFF;  in power_manager_set_profile()
209 		/* check if voltage or frequency change is first */  in power_manager_set_profile()
221 		CLKCTL0->FRO_SCTRIM = sc_trim_192;  in power_manager_set_profile()
222 		CLKCTL0->FRO_RDTRIM = rd_trim_192;  in power_manager_set_profile()
224 		CLKCTL0->FRO_CONTROL &= ~CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK;  in power_manager_set_profile()
239 		 * Reduce frequency first, and then reduce voltage  in power_manager_set_profile()
243 		CLKCTL0->FRO_SCTRIM = sc_trim_96;  in power_manager_set_profile()
244 		CLKCTL0->FRO_RDTRIM = rd_trim_96;  in power_manager_set_profile()
246 		CLKCTL0->FRO_CONTROL &= ~CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK;  in power_manager_set_profile()
283 	/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */  in mimxrt595_evk_init()
284 	SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) |  in mimxrt595_evk_init()
286 	/* Select Data in from Transmit I2S - Flexcomm 3 */  in mimxrt595_evk_init()
287 	SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3);  in mimxrt595_evk_init()
288 	/* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */  in mimxrt595_evk_init()
289 	SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1);  in mimxrt595_evk_init()
291 	/* Set shared signal set 0: SCK, WS from Flexcomm1 */  in mimxrt595_evk_init()
292 	SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(1) |  in mimxrt595_evk_init()
295 	/* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */  in mimxrt595_evk_init()
296 	SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |  in mimxrt595_evk_init()
298 	/* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */  in mimxrt595_evk_init()
299 	SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |  in mimxrt595_evk_init()
302 	/* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */  in mimxrt595_evk_init()
303 	SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1);  in mimxrt595_evk_init()
304 	/* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */  in mimxrt595_evk_init()
305 	SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1);  in mimxrt595_evk_init()
319 	 OCOTP0->OTP_SHADOW[97] = 0x164000;  in mimxrt595_evk_init()
334 	 * However, older EVKs may have pre-production silicon.  in mimxrt595_evk_init()
339 		rd_trim_96 = CLKCTL0->FRO_RDTRIM;  in mimxrt595_evk_init()
357 	memset(__flexspi2_start, 0, __flexspi2_end - __flexspi2_start);  in init_psram_framebufs()