Lines Matching refs:pinmux
15 pinmux = <&iomuxc_gpio_ad_b1_10_adc1_in10>,
26 pinmux = <&iomuxc_gpio_ad_b0_08_enet_ref_clk>;
34 pinmux = <&iomuxc_gpio_ad_b0_09_enet_rx_data1>,
47 pinmux = <&iomuxc_gpio_ad_b0_10_enet_rx_data0>;
56 pinmux = <&iomuxc_gpio_emc_40_enet_mdio>,
65 pinmux = <&iomuxc_gpio_ad_b1_06_gpio1_io22>;
73 pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>;
88 pinmux = <&iomuxc_gpio_sd_b1_00_flexcan1_tx>,
99 pinmux = <&iomuxc_gpio_ad_b1_14_lpi2c1_scl>,
111 pinmux = <&iomuxc_gpio_sd_b1_03_lpi2c4_sda>,
121 /* conflicts with enet pinmux */
124 pinmux = <&iomuxc_gpio_ad_b0_10_lpspi1_sck>,
136 pinmux = <&iomuxc_gpio_ad_b0_07_lpuart1_rx>,
146 pinmux = <&iomuxc_gpio_ad_b0_07_gpio1_io07>;
154 pinmux = <&iomuxc_gpio_ad_b0_06_lpuart1_tx>;
164 pinmux = <&iomuxc_gpio_ad_b1_09_lpuart2_rx>,
175 pinmux = <&iomuxc_gpio_ad_b1_09_gpio1_io25>;
183 pinmux = <&iomuxc_gpio_ad_b1_08_lpuart2_tx>;
194 pinmux = <&iomuxc_gpio_sd_b1_06_sai3_tx_bclk>,
207 pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
215 pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
229 pinmux = <&iomuxc_gpio_ad_b1_07_usdhc1_vselect>;
238 pinmux = <&iomuxc_gpio_sd_b1_04_gpio3_io24>;
245 /* fast pinmux settings for USDHC (over 100 Mhz) */
248 pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
256 pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
270 /* medium pinmux settings for USDHC (under 100 Mhz) */
273 pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
281 pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
295 /* slow pinmux settings for USDHC (under 50 Mhz) */
298 pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
306 pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
323 pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>;
331 pinmux = <&iomuxc_gpio_ad_b0_05_gpio1_io05>;