Lines Matching +full:integration +full:- +full:time

50 The main purpose of these bsim boards is to be test-benches for
51 integration testing of embedded code on workstation/simulation.
52 Integration testing in the sense that the code under test will, at the very
59 The intention being to be able to run tests much faster than real time,
80 - Unit tests:
85 - Integration tests on real HW: Allows testing with the real SW
88   As such can provide better integration coverage than simulation in some cases,
92   They otherwise serve a very similar purpose to simulation integration tests.
93 - Integration tests on workstation (what the POSIX arch and these boards enable)
95   - Using bsim boards: Allow testing the embedded SW (or a subset), including
97     it is possible to test the components interactions and their integration.
98   - Using bsim boards with the BabbleSim Physical layer simulation allows
102   - Using bsim boards, and the `EDTT`_ framework: With the EDTT framework we can
108   - Using Zephyr's :ref:`native_sim <native_sim>` board: It also allows integration testing of
116 - Zephyr's ztest infrastructure and Zephyr's twister:
121   Originally used as a framework for integration testing on target,
142     :figclass: align-center
156 - The `native simulator`_ runner is used to execute the code in your host.
157 - The architecture, SOC and board components of Zephyr are replaced with
159 - The architecture (arch) is the Zephyr :ref:`POSIX architecture<Posix arch>`
163 - The POSIX architecture provides an adaptation from the Zephyr arch API
167 - The SOC ``inf_clock`` layer provides an adaptation to the native simulator CPU "simulation"
170 - The board layer provides all SOC/ IC specific content, including
179   program, command line argument handling, and the overall time scheduling of
189     :figclass: align-center
221 Time and the time_machine
224 Simulated time in bsim boards is in principle fully decoupled from
225 real wall-clock time. As described in
227 simulated time is advanced
231 In general simulation time will pass much faster than real time,
236 The native simulator HW scheduler provides the overall HW event time loop
238 "search for next event", "advance time to next event and execute it" loop,
240 timers having been updated. Events are defined at design time,
257     :figclass: align-center
310 There is a set of one time hooks at different levels of initialization of the HW
321 special timer which can be configured to produce either periodic or one time
324 at specific points in time. This can be combined with Babblesim's tb_defs macros
325 to build quite complex test tasks which can wait for a given amount of time,
345 - Basic arguments: to enable selecting things like trace verbosity, random seed,
349 - The HW models command line arguments: The HW models will expose which
352 - Test (bs_tests) control: To select a test for each embedded CPU,
362 - Endianness: Code will be built for the host target architecture, which is
367 - WordSize: The bsim targets, as well as normal embedded targets are 32 bit