Lines Matching +full:- +full:babblesim

29    https://BabbleSim.github.io
35    https://babblesim.github.io/arch_hw_models.html
38    https://github.com/BabbleSim/native_simulator/blob/main/docs/README.md
41    https://github.com/BabbleSim/native_simulator/blob/main/docs/Design.md
44    https://github.com/BabbleSim/ext_nRF_hw_models/blob/main/docs/README_HW_models.md
50 The main purpose of these bsim boards is to be test-benches for
80 - Unit tests:
85 - Integration tests on real HW: Allows testing with the real SW
93 - Integration tests on workstation (what the POSIX arch and these boards enable)
95   - Using bsim boards: Allow testing the embedded SW (or a subset), including
98   - Using bsim boards with the BabbleSim Physical layer simulation allows
102   - Using bsim boards, and the `EDTT`_ framework: With the EDTT framework we can
108   - Using Zephyr's :ref:`native_sim <native_sim>` board: It also allows integration testing of
116 - Zephyr's ztest infrastructure and Zephyr's twister:
128 Relationship between Zephyr, the native simulator, the nRF HW models and BabbleSim
142     :figclass: align-center
144     Relationship between Zephyr, the native simulator, the nRF HW models and BabbleSim.
156 - The `native simulator`_ runner is used to execute the code in your host.
157 - The architecture, SOC and board components of Zephyr are replaced with
159 - The architecture (arch) is the Zephyr :ref:`POSIX architecture<Posix arch>`
163 - The POSIX architecture provides an adaptation from the Zephyr arch API
167 - The SOC ``inf_clock`` layer provides an adaptation to the native simulator CPU "simulation"
170 - The board layer provides all SOC/ IC specific content, including
189     :figclass: align-center
216 a general introduction to the babblesim HW models and their scheduling are provided.
225 real wall-clock time. As described in
243 Use of babblesim components: tracing, random number generation, logging activity
257     :figclass: align-center
324 at specific points in time. This can be combined with Babblesim's tb_defs macros
345 - Basic arguments: to enable selecting things like trace verbosity, random seed,
349 - The HW models command line arguments: The HW models will expose which
352 - Test (bs_tests) control: To select a test for each embedded CPU,
356 from Babblesim's base/libUtilv1 library. And basic arguments definitions that
362 - Endianness: Code will be built for the host target architecture, which is
367 - WordSize: The bsim targets, as well as normal embedded targets are 32 bit