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1 .. zephyr:board:: mpfs_icicle
6 The Microchip mpfs_icicle board is a PolarFire SoC FPGA based development board with a Microchip MP…
7 The E51 RISC-V CPU can be deployed on the mpfs_icicle board.
8 More information can be found on the `Microchip website <https://www.microchip.com/en-us/product/MP…
16 Applications for the ``mpfs_icicle`` board configuration can be built as usual
19 .. zephyr-app-commands::
20    :board: mpfs_icicle
23 To build the default SMP capable variant
25 .. zephyr-app-commands::
26    :board: mpfs_icicle/polarfire/smp
32 In order to upload the application to the device, you'll need OpenOCD and GDB
33 with RISC-V support.
37 <https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/programming-and-…
39 With the necessary tools installed, you can connect to the board using OpenOCD.
40 To establish an OpenOCD connection run:
42 .. code-block:: bash
45    <softconsole_path>/openocd/bin/openocd --command "set DEVICE MPFS" --file \
46    <softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
49 Leave it running, and in a different terminal, use GDB to upload the binary to
50 the board. You can use the RISC-V GDB from a toolchain delivered with
53 Here is the GDB terminal command to connect to the device
56 .. code-block:: console
58    <softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
59    -ex "target extended-remote localhost:3333" \
60    -ex "set mem inaccessible-by-default off" \
61    -ex "set arch riscv:rv64" \
62    -ex "set riscv use_compressed_breakpoints no" \
63    -ex "load" <path_to_executable>
68 Refer to the detailed overview of :ref:`application_debugging`.