Lines Matching +full:zephyr +full:- +full:based

9 niosv_m board is based on Intel FPGA Design Store Nios® V/m Hello World Example Design system and t…
11 .. code-block:: console
15 	On-Chip Memory Intel® FPGA IP
21 - https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/de…
24 - https://www.intel.com/content/www/us/en/design-example/763960/arria10-niosv-based-helloworld-exam…
31 Please use Intel Quartus Programmer tool to program Nios® V/m processor based system into the FPGA …
35 .. code-block:: console
37 	quartus_pgm -c 1 -m JTAG -o "p;top.sof@1"
39 .. code-block:: console
42 	-c 1 is referring to JTAG cable number connected to the Host Computer.
44 	top.sof is referring to Nios® V/m processor based system SRAM Object File.
46 Download Zephyr elf file and run application
49 To download the Zephyr Executable and Linkable Format .elf file, please use the niosv-download comm…
51 .. code-block:: console
53 	niosv-download -g <elf file>
57 .. code-block:: console
59 	juart-terminal
63 .. code-block:: console
65 	*** Booting Zephyr OS build zephyr-vn.n.nn  ***