Lines Matching +full:out +full:- +full:active +full:- +full:low
6 BL5340 module which is powered by a dual-core Nordic Semiconductor
7 nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a
8 dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
10 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
11 Armv8-M Security Extension, running at up to 128 MHz, referred to as
13 * a secondary Arm Cortex-M33 core, with a reduced feature set, running
20 non-secure partition of the application core on the BL5340 module.
29 * :abbr:`I2C (Inter-Integrated Circuit)`
30 * :abbr:`I2S (Inter-Integrated Sound)`
35 * RADIO (Bluetooth Low Energy and 802.15.4)
39 * :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
62 +-----------+------------+----------------------+
65 | ADC | on-chip | adc |
66 +-----------+------------+----------------------+
67 | CLOCK | on-chip | clock_control |
68 +-----------+------------+----------------------+
69 | FLASH | on-chip | flash |
70 +-----------+------------+----------------------+
71 | GPIO | on-chip | gpio |
72 +-----------+------------+----------------------+
73 | I2C(M) | on-chip | i2c |
74 +-----------+------------+----------------------+
75 | MPU | on-chip | arch/arm |
76 +-----------+------------+----------------------+
77 | NVIC | on-chip | arch/arm |
78 +-----------+------------+----------------------+
79 | QSPI(M) | on-chip | nor |
80 +-----------+------------+----------------------+
81 | PWM | on-chip | pwm |
82 +-----------+------------+----------------------+
83 | RTC | on-chip | system clock |
84 +-----------+------------+----------------------+
86 +-----------+------------+----------------------+
87 | SPI(M/S) | on-chip | spi |
88 +-----------+------------+----------------------+
89 | SPU | on-chip | system protection |
90 +-----------+------------+----------------------+
91 | UARTE | on-chip | serial |
92 +-----------+------------+----------------------+
93 | USB | on-chip | usb |
94 +-----------+------------+----------------------+
95 | WDT | on-chip | watchdog |
96 +-----------+------------+----------------------+
101 +-----------+------------+----------------------+
104 | CLOCK | on-chip | clock_control |
105 +-----------+------------+----------------------+
106 | FLASH | on-chip | flash |
107 +-----------+------------+----------------------+
108 | GPIO | on-chip | gpio |
109 +-----------+------------+----------------------+
110 | I2C(M) | on-chip | i2c |
111 +-----------+------------+----------------------+
112 | MPU | on-chip | arch/arm |
113 +-----------+------------+----------------------+
114 | NVIC | on-chip | arch/arm |
115 +-----------+------------+----------------------+
116 | RADIO | on-chip | Bluetooth, |
118 +-----------+------------+----------------------+
119 | RTC | on-chip | system clock |
120 +-----------+------------+----------------------+
122 +-----------+------------+----------------------+
123 | SPI(M/S) | on-chip | spi |
124 +-----------+------------+----------------------+
125 | UARTE | on-chip | serial |
126 +-----------+------------+----------------------+
127 | WDT | on-chip | watchdog |
128 +-----------+------------+----------------------+
137 An eight-pin GPIO port expander is used to provide additional inputs
143 ----
145 * LED1 (blue) = via TCA9538 port expander channel P4 (active low)
146 * LED2 (blue) = via TCA9538 port expander channel P5 (active low)
147 * LED3 (blue) = via TCA9538 port expander channel P6 (active low)
148 * LED4 (blue) = via TCA9538 port expander channel P7 (active low)
151 ------------
153 * BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low)
154 * BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low)
155 * BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low)
156 * BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low)
157 * BOOT = boot (active low)
166 ------------
174 -------------
176 A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for
179 Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details.
182 ---------------
184 An on-board micro SD card slot is available for use with micro SD cards.
193 ----------------------------------------------------
200 3-Axis Accelerometer
201 --------------------
203 An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C
211 Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip
236 Real-Time Clock
239 A real-time clock is available for accurate time data availability.
246 A 10-bit Digital to Analog Converter is incorporated for generation of
254 - Implementation Defined Attribution Unit (`IDAU`_) on the application
256 used to define secure and non-secure memory maps. By default, all of
259 - Secure boot.
264 The BL5340's application core supports the Armv8-M Security Extension.
268 The BL5340's network core does not support the Armv8-M Security
273 Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg|
276 Applications on the BL5340 module may contain a Secure and a Non-Secure
278 using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure
285 built using TF-M.
287 Building the Secure firmware with TF-M
288 --------------------------------------
290 The process to build the Secure firmware image using TF-M and the
291 Non-Secure firmware image using Zephyr requires the following steps:
293 1. Build the Non-Secure Zephyr application
294 for the application core using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``.
295 To invoke the building of TF-M the Zephyr build system requires the
297 default when building Zephyr as a Non-Secure application.
300 * Build the Non-Secure firmware image as a regular Zephyr application
301 * Build a TF-M (secure) firmware image
307 Depending on the TF-M configuration, an application DTS overlay may
308 be required, to adjust the Non-Secure image Flash and SRAM starting
312 ``-DBOARD=bl5340_dvk/nrf5340/cpunet``.
315 -----------------------------------------
317 The process to build the Secure and the Non-Secure firmware images
321 using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` and
324 2. Build the Non-Secure Zephyr application for the application core
325 using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``.
328 ``-DBOARD=bl5340_dvk/nrf5340/cpunet``.
330 When building a Secure/Non-Secure application for the BL5340's
332 (SPU) configuration to allow Non-Secure access to all CPU resources
333 utilized by the Non-Secure application firmware. SPU configuration
334 shall take place before jumping to the Non-Secure application.
340 and :ref:`application_run`), using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` for
342 ``-DBOARD=bl5340_dvk/nrf5340/cpunet`` for the firmware running
356 The BL5340 has a flash read-back protection feature. When flash
357 read-back protection is active, you will need to recover the chip
359 :ref:`west <west-build-flash-debug>`, run this command for more
360 details on the related ``--recover`` option:
362 .. code-block:: console
364 west flash -H -r nrfjprog --skip-rebuild
373 Here is an example for the :zephyr:code-sample:`hello_world` application running on the
378 .. code-block:: console
380 $ minicom -D <tty_device> -b 115200
387 .. zephyr-app-commands::
388 :zephyr-app: samples/hello_world
401 Try them out:
403 * :zephyr:code-sample:`ble_peripheral`
404 * :zephyr:code-sample:`bluetooth_eddystone`
405 * :zephyr:code-sample:`bluetooth_ibeacon`
410 .. target-notes::
413 https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau
414 …ps://www.ezurio.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-cor…
418 .. _Giantec GT24C256C-2GLI-TR datasheet: https://www.giantec-semi.com/juchen1123/uploads/pdf/GT24C2…
419 …_Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets…
422 .. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf
427 .. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/