Lines Matching refs:PHY
19 Transceiver (PHY). The `PoE Board (B)`_ provides power over Ethernet
114 * - IP101GRI (PHY)
115 - The physical layer (PHY) connection to the Ethernet cable is
118 chip. The connection between PHY and ESP32 is done through the reduced
121 standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100
132 "Activity" statuses of the PHY.
210 The ethernet MAC and PHY under RMII working mode need a common 50 MHz
219 RMII Clock Sourced Externally by PHY
223 IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency
224 multiplication of 25 MHz crystal connected to the PHY. For details, please see
229 :alt: RMII Clock from IP101GRI PHY
232 RMII Clock from IP101GRI PHY
234 Please note that the PHY is reset on power up by pulling the RESET_N signal
236 PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter
246 for transmission line delay, and then supplied to the PHY.
270 IP101GRI (PHY) Interface
273 The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table
278 No. ESP32 Pin (MAC) IP101GRI (PHY)
295 *PHY Reset*
393 clock output on the PHY side, the RESET_N signal to PHY defaults to
396 `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off
575 Enable Ethernet MAC, PHY and MDIO; add these to your device tree overlay:
602 RESET_N (GPIO5) is automatically set high to enable the Ethernet PHY