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7 a `VexRiscv processor <https://github.com/SpinalHDL/VexRiscv>`_
10 <https://github.com/litex-hub/zephyr-on-litex-vexriscv>`_
11 or `LiteX SoC Builder <https://github.com/enjoy-digital/litex>`_
15 `F4PGA toolchain <https://f4pga.org/>`_.
20 <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists>`_
21 or `SDI-MIPI Video Converter <https://github.com/antmicro/sdi-mipi-video-converter>`_.
28 `Migen <https://m-labs.hk/gateware/migen/>`_/`MiSoC SoC builder <https://github.com/m-labs/misoc>`_
34 `LiteX's website <https://github.com/enjoy-digital/litex>`_.
37 written in the `SpinalHDL <https://spinalhdl.github.io/SpinalDoc-RTD/>`_.
44 `VexRiscv's website <https://github.com/SpinalHDL/VexRiscv>`_.
49 `Zephyr on LiteX VexRiscv <https://github.com/litex-hub/zephyr-on-litex-vexriscv>`_
66       git clone https://github.com/litex-hub/zephyr-on-litex-vexriscv.git
71    `this tutorial <https://f4pga-examples.readthedocs.io/en/latest/getting.html>`_.
75    `these instructions <https://github.com/gatecat/prjoxide#getting-started---complete-flow>`_.
120 You can also generate the bitstream using the `official LiteX repository <https://github.com/enjoy-…
127       wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
170 To upload the bitstream to Digilent Arty A7-35 you can use `xc3sprog <https://github.com/matrix-io/…
171 `openFPGALoader <https://github.com/trabucayre/openFPGALoader>`_:
181 Use `ecpprog <https://github.com/gregdavill/ecpprog>`_ to upload the bitstream to SDI-MIPI Video Co…