Lines Matching +full:apt +full:- +full:get

1 .. _litex-vexriscv:
10 <https://github.com/litex-hub/zephyr-on-litex-vexriscv>`_
11 or `LiteX SoC Builder <https://github.com/enjoy-digital/litex>`_
14 vendor-specific and open-source tools, including the
19 `Digilent Arty A7-35T or A7-100T Development Boards
20 <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists>`_
21 or `SDI-MIPI Video Converter <https://github.com/antmicro/sdi-mipi-video-converter>`_.
28 `Migen <https://m-labs.hk/gateware/migen/>`_/`MiSoC SoC builder <https://github.com/m-labs/misoc>`_
29 and provides ready-made system components such as buses, streams, interconnects,
34 `LiteX's website <https://github.com/enjoy-digital/litex>`_.
36 VexRiscv is a 32-bit implementation of the RISC-V CPU architecture
37 written in the `SpinalHDL <https://spinalhdl.github.io/SpinalDoc-RTD/>`_.
38 The processor supports M, C, and A RISC-V instruction
47 bitstream for the FPGA on a Digilent Arty A7-35 Board or SDI-MIPI Video Converter. This can be achi…
49 `Zephyr on LiteX VexRiscv <https://github.com/litex-hub/zephyr-on-litex-vexriscv>`_
64    .. code-block:: bash
66       git clone https://github.com/litex-hub/zephyr-on-litex-vexriscv.git
67       cd zephyr-on-litex-vexriscv
68       git submodule update --init --recursive
70 …Generating the bitstream for the Digilent Arty A7-35 Board requires F4PGA toolchain installation. …
71    `this tutorial <https://f4pga-examples.readthedocs.io/en/latest/getting.html>`_.
73    In order to generate the bitstream for the SDI-MIPI Video Converter, install
75    `these instructions <https://github.com/gatecat/prjoxide#getting-started---complete-flow>`_.
77 #. Next, get all required packages and run the install script:
79    .. code-block:: bash
81       apt-get install build-essential bzip2 python3 python3-dev python3-pip
86    .. code-block:: bash
90 #. Set up the F4PGA environment (for the Digilent Arty A7-35 Board):
92    .. code-block:: bash
102    .. code-block:: bash
104       ./make.py --board=arty --variant=a7-35 --build --toolchain=symbiflow
108    .. code-block:: bash
110       ./make.py --board=arty --variant=a7-100 --build --toolchain=symbiflow
112 #. Generate the bitstream for the SDI-MIPI Video Converter:
114    .. code-block:: bash
116       ./make.py --board=sdi_mipi_bridge --build --toolchain=oxide
120 You can also generate the bitstream using the `official LiteX repository <https://github.com/enjoy-…
125    .. code-block:: bash
127       wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
129 …./litex_setup.py --init --install --user (--user to install to user directory) --config=(minimal, …
131 #. Install the RISC-V toolchain:
133    .. code-block:: bash
136       ./litex_setup.py --gcc=riscv
140    .. code-block:: bash
142 …    ./litex-boards/litex_boards/targets/digilent_arty.py --build --timer-uptime --csr-json csr.json
146    .. code-block:: bash
148 …    ./litex/litex/tools/litex_json2dts_zephyr.py --dts overlay.dts --config overlay.config csr.json
163 .. code-block:: bash
165    west build -b litex_vexriscv path/to/app -DDTC_OVERLAY_FILE=path/to/overlay.dts
170 To upload the bitstream to Digilent Arty A7-35 you can use `xc3sprog <https://github.com/matrix-io/…
173 .. code-block:: bash
175    xc3sprog -c nexys4 digilent_arty.bit
177 .. code-block:: bash
179    openFPGALoader -b arty_a7_100t digilent_arty.bit
181 Use `ecpprog <https://github.com/gregdavill/ecpprog>`_ to upload the bitstream to SDI-MIPI Video Co…
183 .. code-block:: bash
185    ecpprog -S antmicro_sdi_mipi_video_converter.bit
189 .. code-block:: bash
191    litex_term /dev/ttyUSBX --speed 115200 --kernel zephyr.bin