Lines Matching +full:dpll +full:-
17 - ARM Cortex-M4F Processor
18 - 512KB Flash and 320KB RAM
19 - ADC & GPIO headers
20 - SER1, SER2 and SER3
21 - FAN PWM interface
22 - ENE Debug interface
29 +-----------+------------+-------------------------------------+
32 | NVIC | on-chip | nested vector interrupt controller |
33 +-----------+------------+-------------------------------------+
34 | ADC | on-chip | adc controller |
35 +-----------+------------+-------------------------------------+
36 | CLOCK | on-chip | reset and clock control |
37 +-----------+------------+-------------------------------------+
38 | GPIO | on-chip | gpio |
39 +-----------+------------+-------------------------------------+
40 | I2C | on-chip | i2c port/controller |
41 +-----------+------------+-------------------------------------+
42 | PINMUX | on-chip | pinmux |
43 +-----------+------------+-------------------------------------+
44 | PMU | on-chip | power management |
45 +-----------+------------+-------------------------------------+
46 | PSL | on-chip | power switch logic |
47 +-----------+------------+-------------------------------------+
48 | PWM | on-chip | pulse width modulator |
49 +-----------+------------+-------------------------------------+
50 | TACH | on-chip | tachometer sensor |
51 +-----------+------------+-------------------------------------+
52 | SER | on-chip | serial port-polling; |
53 | | | serial port-interrupt |
54 +-----------+------------+-------------------------------------+
55 | WDT | on-chip | watchdog |
56 +-----------+------------+-------------------------------------+
64 on-chip DPLL to generate a resulting EC clock rate of 96MHz/48MHz/24MHz/12MHz.
76 SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/
81 Use SWD with a J-Link
86 .. target-notes::